Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1997-11-26
2001-02-20
Williams, Alexander O. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S659000, C257S691000, C257S774000, C257S758000, C257S748000, C257S660000, C257S759000, C257S698000, C361S816000, C361S792000, C174S255000
Reexamination Certificate
active
06191475
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a substrate upon which integrated circuit components are mounted and, more particularly, to a substrate that reduces electromagnetic emissions and associated electromagnetic interference problems.
2. Description of the Related Art
In the field of electronics, various integrated circuit components, such as microprocessors, are commonly mounted on a substrate. This substrate is typically comprised of ground layers, signal layers, and power layers. The signal layer contains traces that allow the transmission of various signals between the various integrated circuit components positioned on the substrate.
It is well known in the art that signals traveling within these traces can produce electromagnetic emissions, i.e., radiated electrical fields. Electromagnetic interference (“EMI”) can cause several problems, such as malfunctions of nearby electrical devices and interference or degradation of signals traveling along other traces. EMI problems have resulted in the Federal Communications Commission adopting guidelines for maximum allowable levels of electromagnetic emissions in various electronic devices.
It is also well known that faster signal speeds lead to more EMI problems. With the emphasis on increased operating speeds of today's integrated circuit devices, EMI problems also increase.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a substrate for integrated circuit devices is provided that reduces the amount of electromagnetic emissions generated by the integrated circuit devices mounted on the substrate. More particularly, the substrate is comprised of a plurality of layers, which may include signal layers, power layers and ground layers. At least two of these layers each have ground rings that are electrically coupled together by ground stitches. The present invention thus provides a virtual electric ground cage in which high speed signal traces located on the signal layer are embedded within the substrate, thereby preventing or reducing EMI problems when the integrated circuit devices are operating.
In another aspect of the invention, a substrate for mounting integrated circuit devices is provided that comprises a plurality of layers, including signal layers, power layers and ground layers. Each of the layers, other than ground layers, have a ground ring that is electrically coupled to other ground rings by means of ground stitches. The ground stitches are spaced in a random pattern. The randomized spacing of the ground stitches acts to reduce or prevent the generation of standing electromagnetic waves that might otherwise exist if uniform spacing were employed between the ground stitches.
In another aspect of the instant invention, a cover assembly is provided that may be electrically coupled to exposed ground rings on the substrate of the present invention. Electrical coupling between the cover assembly and one or more of the ground rings of the substrate may be provided by electrically conductive clips or gasket material. The cover assembly provides additional shielding that will help prevent or reduce electromagnetic emissions from the integrated circuit devices operating on the substrate.
REFERENCES:
patent: 3916490 (1975-11-01), Sheahan et al.
patent: 4675789 (1987-06-01), Kuwabara et al.
patent: 4827327 (1989-05-01), Miyauchi et al.
patent: 4914503 (1990-04-01), Shirato et al.
patent: 4974041 (1990-11-01), Grinberg
patent: 5119169 (1992-06-01), Kozono et al.
patent: 5283717 (1994-02-01), Hundt
patent: 5315182 (1994-05-01), Sakashita et al.
patent: 5371411 (1994-12-01), Hara et al.
patent: 5401989 (1995-03-01), Kikuchi
patent: 5426405 (1995-06-01), Miller et al.
patent: 5468998 (1995-11-01), Hara et al.
patent: 5491352 (1996-02-01), Tsuji
patent: 5502278 (1996-03-01), Mabboux et al.
patent: 5586011 (1996-12-01), Alexander
patent: 5616952 (1997-04-01), Nakano et al.
patent: 5639989 (1997-06-01), Higgins, III
patent: 5640048 (1997-06-01), Selna
patent: 5672911 (1997-09-01), Patil et al.
patent: 5686699 (1997-11-01), Chu et al.
patent: 5717245 (1998-02-01), Pedder
patent: 5741726 (1998-04-01), Barber
patent: 5831331 (1998-11-01), Lee
patent: 5847466 (1998-12-01), Ito et al.
patent: 5877551 (1999-03-01), Tostado et al.
patent: 5895967 (1999-04-01), Stearns et al.
patent: 5952704 (1999-09-01), Yu et al.
patent: 6020637 (2000-02-01), Karnezos
patent: 6052045 (2000-04-01), Martich
Delaplane Neil C.
Edsall Ron
Lii Mirng-Ji
Mahajan Ravi V.
Skinner Harry G.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Williams Alexander O.
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