Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
1998-07-23
2001-05-29
Picardat, Kevin M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S723000, C438S107000, C438S108000
Reexamination Certificate
active
06239497
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a substrate for packing a semiconductor device, especially a high frequency semiconductor device, and a method for packing the semiconductor device in the packing substrate.
2. Related Arts
FIG. 1
illustrates a conventional semiconductor device packing substrate for packing a high frequency semiconductor device which works at a microwave or millimeter wave band. A first ceramic layer
101
, a metal layer
102
, a second ceramic layer
103
, a wiring layer
104
, and a third ceramic layer
105
are in turn laminated or provided to construct a multilayer ceramic substrate. A portion of the second ceramic layer
103
, the wiring layer
104
and the third ceramic layer
105
is selectively removed off to form a cavity
106
. A semiconductor device
107
on which an electrode pad
108
is provided is mounted on the metal layer
102
exposed by forming the cavity
106
. In this case, the wiring layer
104
is used as an inner layer wiring, and is connected to the electrode pad
108
through a bonding wire
109
. The length of the bonding wire
109
is several hundred &mgr;m, and consequently inductance owing to the bonding wire increases to make transmission of signals difficult at an operation frequency within, especially, a millimeter wave band or higher frequency band. In order to ensure that the cavity has an area into which a semiconductor device is inserted, it is necessary to make the size of the cavity larger than that of the semiconductor device. Therefore, the position where the semiconductor device is packed inside the cavity
106
is varied and the length of the bonding wire
109
is also varied. As a result, various properties of the produced semiconductor devices are also varied, resulting in a drop in the yield rate thereof.
As an example of device in the prior art for that overcomes this problem,
FIG. 2
illustrates a cross section of the main portion of a hybrid integrated circuit device disclosed in Japanese Patent Application Laid-Open No. 5-63136. In this case, a wiring layer
203
is disposed inside a cavity
202
formed in a multilayer substrate
201
, and bump
204
is formed on the wiring layer
203
. With the bump
204
, the wiring layer
203
is electrically connected to an electrode pad
206
of a semiconductor device
205
. Thus, the semiconductor device
205
is electrically connected to the wiring layer
203
with the small inductor element. This prior art example shows the structure of the hybrid integrated circuit device, but does not make any specific packing process clear.
The process for packing a semiconductor device by the aforementioned bump connection includes a process using the contractile force of a resin or the like for bonding, a thermo compression bonding process using compression accompanied with heating for bonding, and a hot melt process of thermally melting bumps for bonding. In all of these processes, however, an expensive position-aligning apparatus is necessary for precisely arranging semiconductor devices in the positions where the semiconductor devices are to be packed.
In the thermo compression bonding or hot melting process, position-aligning must be carried out with heating, and consequently, a large-scale apparatus becomes necessary. When plural elements are packed inside plural cavities in the same substrate, the elements must be packed one by one by using the position-aligning apparatus. For this reason, the packing-work takes a long time, and for semiconductor devices having low heat-resistance, various properties are deteriorated.
The process using the contractile force of a resin or the like has another problem in that a high frequency property is deteriorated because of the fact that dielectric loss and parasite capacitance are enlarged by the resin at an operation frequency within, especially, a millimeter wave band or higher frequency band.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a substrate for packing a semiconductor device for which an expensive and highly precise position-aligning apparatus is not necessary when a wiring layer disposed inside a cavity formed in the substrate is connected to a semiconductor device by means of a bump formed on the wiring layer, and in which any resin which degrades a high frequency property is not used and a plurality of the semiconductor devices can be packed at the same time.
Another object of the invention is to provide a method for packing a semiconductor device in this semiconductor device packing substrate.
Still another object of the invention is to provide a semiconductor device packing substrate that can shorten working time and restrain deterioration of various properties even in a semiconductor device having low heat-resistance.
The semiconductor device packing substrate is a substrate in which a semiconductor device having an electrode pad is packed. This packing substrate comprises a multilayer substrate having a wiring layer for transmitting at least high frequency signal, and a bump for connecting the wiring layer to the semiconductor device. In the substrate, a cavity inside which the semiconductor device is embedded is disposed. The bump is disposed inside the cavity. The size of the cavity is larger by a predetermined size than the size of the semiconductor device, and the upper limit of the predetermined size is the size of the electrode pad disposed on the semiconductor device.
When in this invention the semiconductor device is packed inside the cavity in the semiconductor device packing substrate which is larger by the predetermined size than the semiconductor device so that the cavity can receive the semiconductor device, the side wall of the cavity functions as a guide. Since the upper limit of the predetermined size is the size of the electrode pad disposed on the semiconductor device, the semiconductor device is put on the bump, with a tolerance within the size of the electrode pad. Subsequently, the bump is melted by heating the packing substrate, so that the semiconductor device can move to the right position (e.g., where the device is to be packed by surface tension of the melted bump) even if the device is out of position beforehand. As a result, the semiconductor device is precisely packed in the right position. After heating, the electrode pad formed on the semiconductor device is connected to the wiring layer through the bump.
The semiconductor device can be put at room temperature without use of any especially expensive and precise position-aligning apparatus. Even if a plurality of the cavities inside which semiconductor devices are embedded are formed in the single multilayer substrate, it is unnecessary for the semiconductor devices to be mounted one by one using the position-aligning apparatus as in the prior art, and the plural semiconductor devices can be packed at a time by heating the substrate which is in the state that these elements are packed inside the respective cavities. Therefore, it is possible to shorten working time for packing and restrain deterioration of various properties even in semiconductor devices having low heat-resistance.
Furthermore, the present invention eliminates the problem that high frequency wave property is deteriorated as occurs in the packing process using contractile force of a resin or the like, because the present invention relates to a process wherein the bump is melted by heating to connect the wiring layer to the electrode pad on the semiconductor device.
REFERENCES:
patent: 5616520 (1997-04-01), Nishiuma et al.
patent: 5729038 (1998-03-01), Young et al.
patent: 6046077 (2000-04-01), Baba
patent: 6057597 (2000-05-01), Farnworth et al.
patent: 58-109254 (1983-07-01), None
patent: 4-334049 (1992-11-01), None
patent: 5-63136 (1993-03-01), None
patent: 6-244304 (1994-09-01), None
McGinn & Gibb PLLC
NEC Corporation
Picardat Kevin M.
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