Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With dam or vent for encapsulant
Reexamination Certificate
2000-03-31
2001-05-22
Picardat, Kevin M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With dam or vent for encapsulant
C257S693000, C438S123000, C438S124000
Reexamination Certificate
active
06236108
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a chip-supporting substrate for semiconductor packaging, a semiconductor package, and a process for fabricating the semiconductor package.
2.Description of the Related Art
The number of input/output terminals has increased with improvements in the integration of semiconductors. Accordingly, it has become necessary to provide a semiconductor package having a large number of input/output terminals. In general, the input/output terminals are grouped into a type in which they are arranged around a package in a row and a type in which they are arranged in multiple rows not only around but also inside the package. The former is typified by QFP (quad flat package). When this is made to have a larger number of terminals, terminal pitches must be made smaller, where, in a region of 0.5 mm pitch or less, a high-level technique is required to connect them to the wiring board. The latter array type enables the terminals to be arranged at a relatively large pitch, and hence this is suited for providing multiple pins. Conventionally, PGA (pin grid array) having connecting pins is commonly used as the array type, but this is not suitable for surface packaging because the terminals are connected to the wiring board by insertion. Thus, a package called BGA (ball grid array) has been developed, which enables the surface mounting.
Meanwhile, with the miniaturization of electronic equipment, there is an increasing demand for making the package size much smaller. As a measure to cope with such a demand for smaller size, what is called the chip size package (CSP) has been proposed, which has substantially the same size as a semiconductor chip. This is a package having the connections to an external wiring substrate not around the semiconductor chip but in the mounting region. As examples thereof, it includes a package prepared by bonding a polyimide film having bumps to the surface of a semiconductor chip and providing electrical connections to the chip through gold lead wires, followed by potting with epoxy resin or the like to effect sealing (NIKKEI MATERIALS & TECHNOLOGY 94.4, No. 140, pp.18-19), and a package prepared by forming metal bumps on a provisional substrate at its positions corresponding to the connections to a semiconductor chip and an external wiring substrate and attaching the semiconductor chip by face-down bonding, followed by transfer molding on the provisional substrate (“Smallest Flip-chip-like Package CSP”, The Second VLSI Packaging Workshop of Japan, pp.46-50, 1994).
However, most semiconductor packages hitherto proposed are by no means those which can be adapted to the smaller size and higher integration, can be prevented from package cracking, have a good reliability and also have a good productivity.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor packaging-chip-supporting substrate, a semiconductor package, and a process for fabricating the semiconductor package, which make it possible to produce a small-sized semiconductor package less susceptible to package cracking and having a good reliability.
A first semiconductor packaging chip-supporting substrate of the present invention comprises;
A. an insulating supporting substrate on one surface of which a plurality of wiring are formed; the wiring each having at least i) an inner connection that connects to a semiconductor chip electrode and ii) a semiconductor chip-mounting region;
B. an opening provided in the insulating supporting substrate at its part where each of the wiring is formed on the insulating supporting substrate, which is the part where an outer connection conducting to the inner connection is provided;
C. at least one first through-hole provided between the wiring within the semiconductor chip-mounting region of the insulating supporting substrate;
D. an insulating film formed at the part on which the semiconductor chip is mounted, covering the semiconductor chip-mounting region of the wiring;
E. the insulating film being so provided as to form a hollow between the film and the insulating supporting substrate around the through-hole.
A second semiconductor packaging chip-supporting substrate of the present invention comprises;
A. an insulating supporting substrate on one surface of which a plurality of wiring are formed; the wiring each having at least i) an inner connection that connects to a semiconductor chip electrode and ii) a semiconductor chip-mounting region;
B. an opening provided in the insulating supporting substrate at its part where each of the wiring is formed on the insulating supporting substrate, which is the part where an outer connection conducting to the inner connection is provided;
C. an insulating film formed at the part on which the semiconductor chip is mounted, covering the semiconductor chip-mounting region of the wiring; and
D. at least one metal pattern for maintaining the flatness of the insulating film, formed on the insulating supporting substrate at its part where the insulating film is formed.
The semiconductor package of the present invention comprises the semiconductor packaging chip-supporting substrate of the present invention as described above, a semiconductor chip mounted on the surface of the insulating film of the insulating supporting substrate, and a resin seal that encapsulates the semiconductor chip.
The process for fabricating a semiconductor package comprises the steps of bonding a semiconductor chip to the surface of an insulating film of the semiconductor packaging chip-supporting substrate of the present invention as described above, connecting a semiconductor chip electrode to an inner connection of a wiring by wire bonding, encapsulating the semiconductor chip with resin, and providing, at an opening of the supporting substrate, an outer connection conducting to the inner connection.
As the insulating film, an insulating filmy adhesive may preferably be used.
The opening provided in the insulating supporting substrate may preferably be provided in the insulating supporting substrate at a part where the wiring in the semiconductor chip-mounting region is formed. The opening thus provided in the insulating supporting substrate at the part where the semiconductor chip-mounting region is formed makes it easy to fabricate a small-sized semiconductor package.
The insulating supporting substrate may also be provided with a seal region to be covered with a sealing resin for encapsulating the semiconductor chip, and at least one second through-hole may be provided in the seal region.
In the second semiconductor packaging chip-supporting substrate according to the present invention, at least one first through-hole may be provided between the wiring within the semiconductor chip-mounting region of the insulating supporting substrate, and the insulating film may be so provided as to form a hollow between the film and the insulating supporting substrate around the first through-hole. It is preferable for a plurality of metal pattern to be formed, and for the distance between thereof to be 1 millimeter or less. More specifically, it is preferred that at least one metal pattern is formed within the range of a 1 millimeter radius from an arbitrary point. Such a plurality of metal patterns may preferably be arranged uniformly.
REFERENCES:
patent: 6064111 (2000-05-01), Sota et al.
Awano Yasuhiko
Ichimura Shigeki
Inoue Fumio
Iwasaki Yorio
Miyata Koji
Hitachi Chemical Company Ltd.
Pennie & Edmonds LLP
Picardat Kevin M.
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