Substrate for electronic packaging, pin jig fixture

Details Substrate for electronic packaging, pin jig fixture Substrate for electronic packaging, pin jig fixture

2000-06-22

2002-09-10

Cunio, Kamand (Department: 2827)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S256000, C174S258000, C174S262000, C361S809000, C029S846000, C428S901000

Reexamination Certificate

active

06448510

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to substrates for electronic packaging including inter alia ball grid array packaging (BGA), chip size/scale package (CSP) and multi-chip/module packaging (MCP/CM), and a process of manufacturing therefor. In addition, the invention relates to a fire for masking purposes, and a process using the fixture for preparing a selectively patterned valve metal surface.
BACKGROUND OF THE INVENTION
Conventional electronic packaging includes a discrete substrate on which one or more integrated circuit chips (ICCs) are mounted on its topside, for example. in the case of BGA, as illustrated and described in U.S. Pat. No. 5,355,283 to Marrs et al. The discrete substrate can be of a wide range of materials including inter alia aluminum and irrespective of its material, through holes are drilled between its topside and underside. In the case of an aluminum substrate, each hole is initially anodized to create an insulating sleeve prior to the insertion of a metal pin, thereby enabling electrical and thermal communication between its topside and underside.
Depending on the intended complexity of an electronic package, a multi-layer interconnect structure can be interdisposed between the ICCs and the substrate, for example, as illustrated and described in U.S. Pat. No. 5,661,341 to Neftin. Such a multi-layer interconnect structure has one or more aluminum layers, each layer being deposited on a previously prepared topside and typically having a thickness in the order of between about 0.5 &mgr;m and about 20 &mgr;m.
Conventional masking for area selective anodization purposes is a relatively complicated and expensive process including the application and subsequent removal of an inert masking layer using photolithography and deposition techniques, the layer being in the form of a photo material, a dense oxide layer, a tantalum metal thin film, and the like.
SUMMARY OF THE INVENTION
In accordance with a first aspect of the present invention, there is provided a substrate for electronic packaging, the substrate comprising a discrete, generally prismatoid, initially electrically conductive valve metal solid body with a pair of opposing major surfaces, said body having one or more original valve metal filled vias substantially perpendicular to said major surfaces, said filled vias being spaced apart and individually electrically isolated by a porous oxidized body portion therearound.
A substrate in accordance with the present invention can be fabricated from suitable valve metal blanks of aluminum, titanium, or tantalum, and preferably inter alia Al5052, Al5083, Al1100, Al1145, and the like. Such a substrate can be readily manufactured to customer requirements in terms of a desired filled via pattern; electrical properties; the relative proportions of the original valve metal filled vias and the porous oxidized body portions; thermo-mechanical properties such as thermal coefficient of expansion (TCE), substrate strength. Young modulus, elasticity; thermal properties such as thermal conductivity coefficient, and other factors. Such a substrate can be manufactured with a minimum filled via diameter of about 25 &mgr;mm and a minimum center to center distance between adjacent filled vias of about 50 &mgr;m, thereby affording high miniturization and high fluency operation of electronic packaging.
In accordance with a second aspect of the present invention, there is provided a process for manufacturing a discrete substrate fur electronic packaging, the process comprising the steps of:
(a) providing a discrete, generally prismatoid, initially electrically conductive valve metal, solid blank having a pair of opposing major surfaces, the blank having a plurality of spaced apart generally cylindrical through sections, each through section having end surfaces and extending substantially perpendicular to the pair of opposing major surfaces;
(b) selectively masking both end surfaces of one or more of the through sections; and
(c) porously oxidizing the blank whereupon a porous oxidized portion forms around a through section whose both end surfaces are masked thereby retaining the through section as an original metal valve filled via.
A process of manufacturing a discrete substrate for electronic packaging in accordance with the present invention involves a low number of steps and is suitable for Be area panel production. During or post anodization suitable can be impregnated into the blank's oxidized portions which typically thicken and therefore require planarization to restore them to their original thickness.
The porous anodization can be either one- or two-sided depending on the thickness of the generally cylindrical through sections some of which are to be retained as original valve metal filled vias. Typically, one-sided porous anodization can be applied to a maximum through section thickness of about 150 &mgr;m whilst two-sided porous anodization can be applied to a maximum through section thickness of about 300 &mgr;m. One- and two-sided porous anodization can be effected in a conventional manner, for example, as illustrated and described in U.S. Pat. No. 5,661,341 to Neftin.
In accordance with a third aspect of the present invention, there is provided a pin jig fixture for mechanically masking a valve metal surface, the pin jig comprising an anodization resistant bed of pins each having a leading end surface for intimate juxtaposition against a portion of the metal surface whereby said portion is masked.
A pin jig fixture in accordance with the present invention enables the simultaneous masking of one or more portions of a valve metal surface by its mechanical clamping thereagainst. Typically, the pins have planar end surfaces which are co-planar, however, a jig pin fixture can have pins of different lengths whereby their end surfaces lie on different parallel planes. The bed of pins can be fabricated from any suitable anodization resistant material including ceramics, valve metals, and the like.
The pin jig fixture can be preferably employed to directly oxidize those non-masked portions immediately surrounding the metal surface portions masked thereby, in which case, the pins are fabricated from valve metal and have electrically conductive end surfaces connectable to a power source. In addition, the pin jig fixture advantageously negates the need for an otherwise redundant portion of a substrate, such portion conventionally being initially used for connection to an electrical source and which is subsequently removed.
In accordance with a fourth aspect of the present invention, there is provided a process for preparing a selectively patterned valve metal surface, the process comprising the steps of:
(a) providing a pin jig fixture having an anodization resistant bed of pins each having a leading end surface;
(b) intimately juxtaposing leading end surfaces against a valve metal surface to mask portions thereof; and
(c) anodizing the masked metal surface.


REFERENCES:
patent: 2305990 (1942-12-01), Prest
patent: 3622473 (1971-11-01), Ohta et al.
patent: 4045302 (1977-08-01), Gibbs et al.
patent: 4285781 (1981-08-01), Le Rouzic et al.
patent: 4445981 (1984-05-01), Ishii et al.
patent: 5022976 (1991-06-01), Roll et al.
patent: 5045921 (1991-09-01), Lin et al.
patent: 5112668 (1992-05-01), Rabiet et al.
patent: 5229549 (1993-07-01), Yamakawa et al.
patent: 5262226 (1993-11-01), Yoshida
patent: 5355283 (1994-10-01), Marrs et al.
patent: 5580825 (1996-12-01), Labunov et al.
patent: 5629835 (1997-05-01), Mahulikar et al.
patent: 5661341 (1997-08-01), Neftin
patent: 5767575 (1998-06-01), Lan et al.
patent: 5774336 (1998-06-01), Larson
patent: 5946600 (1999-08-01), Hurwitz et al.
patent: 5952083 (1999-09-01), Parthasarathi et al.
patent: 6046499 (2000-04-01), Yano et al.
patent: 6235181 (2001-05-01), Kinard et al.
patent: 6236112 (2001-05-01), Horiuchi et al.
patent: 6262477 (2001-07-01), Mahulikar et al.
patent: 0335291 (1989-10-01), None
patent: 0563744 (1993-10-01), None
patent: 2459557 (1981-01-01), None
patent: 2466103 (1981-04-01), None
patent: 2080630 (198

Affiliated with

Also associated with

Rating

Substrate for electronic packaging, pin jig fixture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Substrate for electronic packaging, pin jig fixture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Substrate for electronic packaging, pin jig fixture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2849901