Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With stress relief
Reexamination Certificate
1998-04-15
2002-12-31
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With stress relief
C257S688000, C257S666000, C257S780000
Reexamination Certificate
active
06501157
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to semiconductor chip packaging. More particularly, the present invention relates to semiconductor package assemblies configured to accept both flip-chip and wirebond semiconductor chips.
2. The Relevant Technology
Integrated circuits are currently manufactured by an elaborate process in which semiconductor devices, insulating films, and patterned conducting films are sequentially constructed in a predetermined arrangement on a semiconductor substrate. In the context of this document, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term “substrate” refers to any supporting structure including but not limited to the semiconductor substrates described above. The term “electronic component” refers to any device or structure which may be connected to and respond to an electrical power or signal source, and includes, but is not limited to, semiconductor dies, semiconductor substrates, and integrated circuits as described above.
Semiconductor dies are commonly packaged to produce devices in a form for convenient use by consumers. Packaging steps are conducted to provide signal and power distribution to and from the semiconductor die, to dissipate heat from the semiconductor die, and to physically protect the semiconductor die. There is an ongoing effort in the semiconductor industry to reduce packaging costs, to improve electrical and thermal performance, and to reduce size.
An important packaging process is that of mounting and electrically connecting a semiconductor die to a mounting substrate such as a printed circuit board. A printed circuit board has a series of internal and external printed wires for electrically connecting two or more semiconductor dies or other electronic components that are mounted or attached thereto. Commonly, a semiconductor die is mounted over a receiving member that is in turn attached to the mounting substrate. Often, the receiving member is also a printed circuit board. The receiving member has a series of internal electrically conductive traces, each of which extends between at least two contact sites. One contact site is positioned to provide electrical connection with a bond pad on the semiconductor die, while the other contact site is located so as to provide electrical connection with the mounting substrate. Thus, a semiconductor package assembly formed according to the above-described process includes a semiconductor die mounted over a receiving member, which is in turn attached to a mounting substrate.
Semiconductor dies are structured according to one of at least two available designs: wirebond and flip-chip. Wirebond semiconductor dies have a set of bond pads arrayed on a face thereof. These semiconductor dies are packaged on a mounting substrate such that the face having the bond pads faces away from the receiving member and the mounting substrate. The bond pads are then wired to corresponding contact sites on the receiving member. In contrast, the bond pads of a flip-chip semiconductor die are arrayed on the opposite face. The face of a flip-chip that has the bond pads is disposed directly on the receiving member. An array of solder balls or other conductive material provides electrical connection between the bond pads of the flip-chip and the contact sites of the receiving member.
Manufacturers may find it commercially desirable to produce any specific integrated circuit according to both the wirebond and flip-chip designs. For example, one customer may demand a flip-chip, while another customer may be satisfied with a wirebond semiconductor die. However, such dual design of integrated circuits has required two corresponding receiving members, one configured to receive a flip-chip, and the other to receive the wirebond semiconductor die. Dual design of receiving members is expensive for the manufacturer—it requires increased inventory and redundant design and effort. The cost of producing and keeping in inventory dual receiving members may make production of dually designed integrated circuits prohibitive, thereby preventing market demand from being satisfied. It will be appreciated that a receiving member that is capable of receiving either a flip-chip or a wirebond semiconductor die, as needed, would be advantageous.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor package assembly that is configured to include or receive either a flip-chip or a wirebond semiconductor die. According to the invention, one receiving member design is sufficient to provide packaging for both the flip-chip and wirebond designs of a semiconductor die. Thus, a single receiving member can be used with either a flip-chip or wirebond semiconductor die according to customer demand or other design constraints. Various embodiments, of the invention include a receiving member alone or a receiving member in combination with one or both of a mounting substrate and an electronic component.
The receiving member according to the invention has a component receiving surface with a component receiving region thereon. The component receiving region is configured to receive an electronic component. The component receiving region is defined and bounded by a perimeter that corresponds to the periphery of the electronic component. Accordingly, an electronic component mounted over a component receiving surface will be aligned with and substantially positioned over the component receiving region.
According to a preferred embodiment of the invention, a plurality of first contact sites and a plurality of second contact sites are arrayed on the component receiving surface. The first contact sites are positioned within the perimeter of the component receiving region, and provide electrical connection with the bond pads of a flip-chip. The second contact sites are positioned outside of the perimeter, and provide electrical connection with the bond pads of a wirebond electronic component. Electrically conductive traces within the receiving member connect the first contact sites and the second contact sites with terminal contact sites positioned on a surface of the receiving member. Each trace connects one corresponding first contact site, one corresponding second contact site, and one corresponding terminal contact site.
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Smith Matthew
Workman & Nydegger & Seeley
Yeusikov V.
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