Substrate engineering for optimum CMOS device performance

Details Substrate engineering for optimum CMOS device performance Substrate engineering for optimum CMOS device performance

2006-12-12

2006-12-12

Andujar, Leonardo (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With specified crystal plane or axis

C257S628000, C257S367000, C257S368000, C257S369000

Reexamination Certificate

active

07148559

ABSTRACT:
An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a <001> direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a <110> direction and the at least one NFET has a current flow in a <100> direction. The <110> direction is perpendicular to the <100> direction. A method of fabricating such as integrated semiconductor structure is also provided.

REFERENCES:
patent: 5317175 (1994-05-01), Throngnumchai
patent: 6245615 (2001-06-01), Noble et al.
patent: 6368903 (2002-04-01), Bryant et al.
patent: 6483171 (2002-11-01), Forbes et al.
patent: 2001/0026006 (2001-10-01), Noble et al.
patent: 2002/0014666 (2002-02-01), Ohmi et al.
patent: 2002/0063292 (2002-05-01), Armstrong et al.
patent: 2002/0173093 (2002-11-01), Juengling
patent: 2002/0185676 (2002-12-01), Momose
patent: 51453/68 (1968-10-01), None
patent: 62-92361 (1987-04-01), None
patent: 01076755 (1987-09-01), None
patent: 64-7675 (1989-03-01), None
patent: 64-70748 (1989-03-01), None
patent: 01076755 (1989-03-01), None
patent: 2181948 (1990-07-01), None
patent: 7-183488 (1995-07-01), None
patent: 411354394 (1999-12-01), None

Affiliated with

Also associated with

Rating

Substrate engineering for optimum CMOS device performance does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Substrate engineering for optimum CMOS device performance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Substrate engineering for optimum CMOS device performance will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3658468