Substrate configurable JTAG ID scheme

Details Substrate configurable JTAG ID scheme Substrate configurable JTAG ID scheme

2006-10-31

2006-10-31

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C365S103000, C365S174000

Reexamination Certificate

active

07131033

ABSTRACT:
A circuit generally comprising a core circuit and a test access port circuit. The core circuit may be configurable among a plurality of functions in response to a signal. The test access port circuit may be configured to determine an identification value in response to the signal.

REFERENCES:
patent: 4558345 (1985-12-01), Dwyer et al.
patent: 4808844 (1989-02-01), Ozaki et al.
patent: 4985641 (1991-01-01), Nagayama et al.
patent: 4990800 (1991-02-01), Lee
patent: 5048021 (1991-09-01), Jarwala et al.
patent: 5119163 (1992-06-01), Ishihara et al.
patent: 5161124 (1992-11-01), Love
patent: 5221890 (1993-06-01), Shyu et al.
patent: 5295110 (1994-03-01), Sakakibara
patent: 5303180 (1994-04-01), McAdams
patent: 5353250 (1994-10-01), McAdams
patent: 5355369 (1994-10-01), Greenberger et al.
patent: 5361003 (1994-11-01), Roberts
patent: 5373470 (1994-12-01), Jones, Jr.
patent: 5379261 (1995-01-01), Jones, Jr.
patent: 5412333 (1995-05-01), Okunaga
patent: 5467304 (1995-11-01), Uchida et al.
patent: 5530391 (1996-06-01), Bohme et al.
patent: 5544115 (1996-08-01), Ikeda
patent: 5553022 (1996-09-01), Weng et al.
patent: 5589783 (1996-12-01), McClure
patent: 5594442 (1997-01-01), Paulos et al.
patent: 5625595 (1997-04-01), Ikeda
patent: 5642307 (1997-06-01), Jernigan
patent: 5646451 (1997-07-01), Freyman et al.
patent: 5682105 (1997-10-01), Fujima
patent: 5751173 (1998-05-01), McMahon et al.
patent: 5754879 (1998-05-01), Johnston
patent: 5787012 (1998-07-01), Levitt
patent: 5831925 (1998-11-01), Brown et al.
patent: 5880596 (1999-03-01), White
patent: 5896404 (1999-04-01), Kellogg et al.
patent: 5920227 (1999-07-01), An
patent: 5926053 (1999-07-01), McDermott et al.
patent: 5982043 (1999-11-01), Iwata
patent: 6034539 (2000-03-01), Hwang
patent: 6111441 (2000-08-01), Hartley et al.
patent: 6161213 (2000-12-01), Lofstrom
patent: 6225818 (2001-05-01), Park et al.
patent: 6324088 (2001-11-01), Keeth et al.
patent: 6378090 (2002-04-01), Bhattacharya
patent: 6525560 (2003-02-01), Trimberger et al.
patent: 6581190 (2003-06-01), Dixon et al.
patent: 6600686 (2003-07-01), Huh et al.
“A Novel Robust and Low Cost Stack Chips Package and Its Thermal Performance”, By Soon-Jin Cho et al., IEEE Transaction on Advanced Packaging, vol. 23, No. 2, May 2000, pp. 257-265.
“A Compact V-Band 3-D MMIC Single-Chip Down-Converter Using Photosensitive BCB Dielectric Film”, By Kenjiro Nishikawa et al., IEEE Transactions on Microwave Theory and Techniques, vol. 47, No. 12, Dec. 1999, pp. 2512-2518.
“A 6.8ns 1Mb ECL I/O BiCMOS Configurable SRAM”, By Bob Kertis et al., 1990 Symposium on VLSI circuits, pp. 39-40.
“IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Std. 1149.1-2001, Jul. 23, 2001, pp. 1-200.

Affiliated with

Also associated with

Rating

Substrate configurable JTAG ID scheme does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Substrate configurable JTAG ID scheme, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Substrate configurable JTAG ID scheme will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3666980