Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-06-01
2002-08-06
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S697000, C257S737000, C257S774000, C438S014000, C438S015000
Reexamination Certificate
active
06429453
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a semiconductor device, and more particularly to a substrate for performing a burn-in test of integrated circuit chips (IC chips) and a method of manufacturing a good die array utilizing the substrate.
Standard integrated circuit chips, in general, are subjected to various tests in order to determine the reliability of the chips before distributing the chips for use. Briefly, there are two important reliability tests: one is an electrical characteristic test in which all input and output terminals are connected to a test signal generator to verify the transferring characteristics between the signals coming in and out at the terminals; the other is a burn-in test in which a given chip is exposed to overstress conditions of higher than normal operating temperatures and voltages to verify its lifetime and to detect defects.
As an example, the burn-in test for a dynamic random access memory chip has appreciated as a useful method to verify the reliability of memory circuit elements such as memory cells and signal lines. During the burn-in test, defects latent in a dynamic random access memory chip result in the destruction of gate oxide films of MOS transistors and shortening between multi-leveled conduction layers. These defective chips are abandoned as inferior and non-defective chips are selected as a known good die instead.
In such a burn-in test, the defective chips abandoned as inferior are about 5% to 10% of the tested chips. Therefore, since the defective chips are already packaged, the conventional technologies for fabricating the known good die require the use of many materials and the unwanted investment of unnecessary cost.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a substrate for a burn-in test of the integrated circuit chip in a state of non-packaged chip, which obviates the use of unnecessary materials and the investment of unnecessary cost in manufacturing the known good die.
It is another object of the invention to provide a method for producing the known good die, which eliminates the use of unnecessary materials and the investment of unnecessary cost.
To achieve the above objectives of this invention, there is provided a substrate for burn-in test of an integrated circuit chip with a plurality of bonding pads so as to verify whether the chip is a known good die. The substrate includes a body having a plurality of through holes; a plurality of metal lines electrically connected to the bonding pads of the integrated circuit chip and formed on one surface of the body; a plurality of pins each inserted into the respective corresponding holes and thus electrically connected to the respective corresponding metal lines and also projected from a surface opposite to the surface on which the metal lines are formed, the pins being electrically connected to an exterior electrical circuit.
To achieve another object of this invention, there is provided one method for manufacturing a known good die including the steps of: providing a substrate including a body, a plurality of metal lines formed on one surface of the body and a plurality of conductive pins which project from the other surface of the body and electrically connect with the metal lines; forming an adhesive film having a higher melting point than that of an normal operating temperature of the die, on the surface on which the metal lines of the body are formed; adhering an integrated circuit chip having a plurality of bonding pads thereon and a plurality of bumps formed on the bonding pads, onto the surface of the body through the adhesive film such that the bumps are aligned with the metal lines of the substrate; carrying out a burn-in test of the integrated circuit chip, and separating the chip from the substrate by vaporizing the adhesive films.
There is also another method for manufacturing a known good die including the steps of: providing a substrate including a body, a plurality of metal lines formed on one surface of the body and a plurality of conductive pins which project from the other surface of the body and electrically connect with the metal lines; adhering an integrated circuit chip having a plurality of bonding pads, a plurality of conductive elements bonded on the bonding pads, and a plurality of solder-containing metals having a melting point higher than a normal operating temperature of the known-good die and attached to the conductive elements, onto the surface on which the metal lines of the body are formed, thereby to connect the bonding pads to the metal lines of the substrate; carrying out a burn-in test of the chip; and separating the chip from the substrate by melting the solder-containing metals.
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Hyundai Electronics Industries Co,. Ltd.
Tran Minh Loan
Ware Fressola Van Der Sluys & Adolphson LLP
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