Submicron planarization process with passivation on metal line

Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device

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430317, 156643, 156646, 156653, 437228, 437235, 437238, G03F 726

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active

053668502

ABSTRACT:
A passivation layer is provided over a conductive layer for contacting the active elements of semiconductor device structures in and on a semiconductor substrate. The passivation and conductive layers are patterned simultaneously. A thin oxide layer is deposited over the patterned conductive and passivation layers. The thin oxide layer is covered with a spin-on-glass layer to fill the valleys of the patterned conductive and passivation layers. The spin-on-glass layer is cured and then partially blanket anisotropically etched through its thickness and through the thin oxide layer to the underlying passivation layer at its highest point leaving spin-on-glass layer portions in the valleys. A top dielectric layer is deposited over the spin-on-glass layer to complete the planarization. Alternatively, an anisotropic oxide is deposited over patterned conductive lines of an integrated circuit. This anisotropic oxide deposits preferentially on the horizontal surfaces and relatively little on the vertical surfaces. The anisotropic oxide layer is covered with a spin-on-glass layer to fill the valleys of the patterned conductive layer. The spin-on-glass layer is cured and then partially blanket anisotropically etched through its thickness to the underlying anisotropic layer at its lowest point leaving spin-on-glass layer portions in the valleys. A top dielectric layer is deposited over the spin-on-glass layer to complete the planarization.

REFERENCES:
patent: 4676867 (1987-06-01), Elkins
patent: 4775550 (1988-10-01), Chu
patent: 4885262 (1989-12-01), Ting
patent: 5003062 (1991-03-01), Yen
patent: 5266525 (1993-11-01), Morozumi

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