Sublithographic patterning method incorporating a...

Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device

Reexamination Certificate

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C430S314000

Reexamination Certificate

active

07960096

ABSTRACT:
A method of implementing sub-lithographic patterning of a semiconductor device includes forming a first set of patterned features with a single lithography step, the initial set of patterned features characterized by a linewidth and spacing therebetween; forming a first set of sidewall spacers on the first set of patterned features, and thereafter removing the first set of patterned features so as to define a second set of patterned features based on the geometry of the first set of sidewall spacers; and performing one or more additional iterations of forming subsequent sets of sidewall spacers on subsequent sets of patterned features, followed by removal of the subsequent sets of patterned features, wherein a given set of patterned features is based on the geometry of an associated set of sidewall spacers formed prior thereto, and wherein a final of the subsequent sets of patterned features is characterized by a sub-lithographic dimension.

REFERENCES:
patent: 6063688 (2000-05-01), Doyle et al.
patent: 6194268 (2001-02-01), Furukawa et al.
patent: 6884735 (2005-04-01), Okoroanyanwu et al.
patent: 2006/0273456 (2006-12-01), Sant et al.
patent: 2006/0281266 (2006-12-01), Wells

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