Sub-system power noise suppression design procedure

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07490306

ABSTRACT:
Aspects of the disclosure provide methods and systems to design a distributed discrete capacitor bank incorporating power plane capacitance to concentrate the suppression of AC coupling to the frequencies caused by clocks and signal transitions. Aspects of the disclosure provide a procedure for designing a distributed capacitor bank from a combination of bulk capacitors, ceramic capacitors and/or plane capacitance that provides the desired impedance Z to suppress noise at all desired frequencies.

REFERENCES:
patent: 2002/0169590 (2002-11-01), Smith et al.
patent: 2003/0222655 (2003-12-01), Gauthier et al.
patent: 2004/0088661 (2004-05-01), Anderson et al.

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