Sub-pipelined and pipelined execution in a VLIW

Details Sub-pipelined and pipelined execution in a VLIW Sub-pipelined and pipelined execution in a VLIW

2005-05-17

2005-05-17

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Long instruction word

C712S209000

Reexamination Certificate

active

06895494

ABSTRACT:
A subpipelined translation embodiment provides binary compatibility between current an future generations of DSPs. When retrieved from memory an entire fetch packet is assigned an operating mode (base instruction set or migrant instruction set) according to the current execution mode. The fetch packets from the instruction memory are parsed into execute packets and sorted by execution unit (dispatched) in a datapath shared by both execution modes (base and migrant). The two execution modes have separate control logic. Instructions from the dispatch datapath are decoded by either base architecture decode logic or the migrant architecture decode logic, depending on the execution mode bound to the parent fetch packet. Code processed by the migrant and base decode pipelines produces machine words that are selected by a multiplexer. The multiplexer is controlled by the operating mode bound to the fetch packet that produced the machine word. The selected machine word controls a global register file, which supplies operands to all hardware execution units and accepts results of all hardware execution units.

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