Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-11-06
2007-11-06
Schillinger, Laura M. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S613000, C438S200000
Reexamination Certificate
active
10403439
ABSTRACT:
A method to form a very low resistivity interconnection in the manufacture of an integrated circuit device is achieved. A bottom conductive layer is formed overlying a substrate. The bottom conductive layer creates a first electrical coupling of a first location and a second location of the integrated circuit device. A dielectric layer is formed overlying the bottom conductive layer. A top conductive layer is formed overlying the dielectric layer. The top conductive layer is coupled to the bottom conductive layer through openings in the dielectric layer to form a second electrical coupling of the first location and the second location. A metal wire is bonded to the top conductive layer to form a third electrical coupling of the first location and the second location to complete the very low resistivity interconnection in the manufacture of the integrated circuit device.
REFERENCES:
patent: 4434347 (1984-02-01), Kurtz et al.
patent: 4891333 (1990-01-01), Baba et al.
patent: 5032889 (1991-07-01), Murao et al.
patent: 5495667 (1996-03-01), Farnworth et al.
patent: 5578841 (1996-11-01), Vasquez et al.
patent: 5673845 (1997-10-01), Ball
patent: 5869357 (1999-02-01), Zambrano
patent: 6258706 (2001-07-01), Yiu et al.
patent: 6373100 (2002-04-01), Pages et al.
patent: 6419145 (2002-07-01), Ball
patent: 6569758 (2003-05-01), Jorger et al.
patent: 6852616 (2005-02-01), Sahara et al.
patent: 2003/0080416 (2003-05-01), Jorger et al.
patent: 2003/0190774 (2003-10-01), Jorger et al.
patent: 0 418802 (1990-09-01), None
patent: 2095904 (1982-02-01), None
patent: 06061288 (1994-04-01), None
patent: 2000133730 (2000-12-01), None
Jórger Wolfgang
Keller Michael
Stellberger Achim
Ackerman Stephen G.
Dialog Semiconductor GmbH
Pike Rosemary L.S.
Saile Ackerman LLC
Schillinger Laura M.
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