Sub-half-micron multi-level interconnection structure and proces

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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438625, 438637, H01L 21441

Patent

active

059813741

ABSTRACT:
The present invention relates to the field of semiconductor manufacturing, and more specifically to methods of forming sub-half-micron multi-level interconnect structures for integrated circuits. The inventive structure and process are spike free and that has resulted in improved circuit performance, reliability and process yields. The inventive structure and process have a plurality of insulator layers where each of the adjoining insulator layers are of a different material.

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