Semiconductor device manufacturing: process – Masking
Reexamination Certificate
2001-10-25
2004-02-03
Eckert, George (Department: 2815)
Semiconductor device manufacturing: process
Masking
C438S945000, C438S717000, C438S725000
Reexamination Certificate
active
06686300
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
This invention is in the field of integrated circuit manufacture, and is more specifically directed to the photolithographic patterning and etching of elements such as transistor gates and dielectric features in integrated circuits.
A fundamental trend in the field of monolithic integrated circuits is the ever-decreasing reduction of critical feature sizes. Smaller feature sizes, of course, enable the implementation of a higher density of active devices for a given chip area, resulting in greater functionality and lower manufacturing cost. Smaller feature sizes also typically result in improved device performance. In metal-oxide-semiconductor (MOS) integrated circuits, for example, smaller transistor gate widths translate directly to shorter transistor channel lengths. As is well known in the art, shorter transistor channel lengths provide improved gain and drive for MOS transistors.
In MOS technology, one may derive a Figure of Merit (FOM) based upon the inverse relationship of drive current to gate capacitance and to supply voltage:
FOM
∝
I
drive
C
gate
V
d
As such, improvements in the FOM parameter involve increased drive current I
drive
relative to the device gate capacitance C
gate
and drain voltage V
d
. According to conventional technology, an increase in FOM is generally provided by a reduction in gate electrode width and the corresponding transistor channel length.
Of course, a countervailing factor to increasing drive current is an increase in leakage current with decreasing gate width.
FIG. 1
illustrates the relationship of drive current I
drive
to subthreshold (off-state) leakage current I
leak
, for a given device threshold voltage. In some circuit applications, however, one may accept the tradeoff of increased leakage in order to attain the improved drive current. According to conventional techniques, to obtain higher drive current (at a cost of increased leakage current) and move along curve
2
from point P
1
to point P
2
for a given technology (i.e., process parameters such as gate oxide, etc.), it is typically necessary to reduce the feature size of gate electrode width, or use additional mask steps to provide complex ion implants
As is well known in the art, however, the minimum feature size that may be produced in an integrated circuit is limited by the photolithography process. In particular, a minimum patternable feature size is defined, for a given photolithography process, by the smallest width line of photoresist that may be reliably formed after exposure and developing. This size is generally referred to as the critical dimension, or CD. Typically, the CD depends upon the photoresist material used, the planarity of the surface being patterned, and the wavelength of light used to expose the photoresist. If one attempts to pattern a line at a width below the process CD, the line will not be manufacturable due to non-reproducibility, non-uniformity, loss of CD control, missing lines, lack of process margin, and the like.
Other techniques for improving drive current for a given technology and photolithography CD are also known. One way is to perform a masked threshold adjust implant into the channel region of the device, reducing the threshold voltage in surface channel MOS devices. Another approach is to perform masked lightly-doped drain implants to provide implants of varying energies, further tailoring the effective channel length. As evident from this description, these alternative approaches involve at least one additional photolithography step (two in the case of CMOS), adding process cost and process complexity.
Similar concerns are also present in the formation of small insulator features in integrated circuits. As known in the art, small features of silicon dioxide, silicon nitride, and the like are often useful at various stages in the process. For example, patterned insulator films are used to define active regions (“inverse moat” locations) of the integrated circuit. A patterned insulator film may also be used, instead of photoresist, as a hard mask layer, in which case the feature size of the patterned insulator film may become critical. Further, in many modem processes, a so-called “damascene” approach is used to define conductors; this technique involves the patterned etch of an insulator film to form openings into which the conductor layer is then deposited, effectively inlaying the conductor into the desired pattern.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a transistor having improved drive current for a given technology critical dimension feature size.
It is a further object of the present invention to provide a method of forming such a transistor without requiring a change in the photolithography process other than a mask change.
It is a further object of the present invention to provide such a transistor and method with minimal added manufacturing cost.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
The present invention may be implemented by the photolithographic patterning of a layer of photoresist, for example for patterning a critical dimension such as transistor gates. The patterning is performed with a mask having a pattern with varying line widths. At selected positions along the pattern, the line width is at or above the critical dimension; at locations between these positions, the line width is below the critical dimension. The ratio and periodicity of critical dimension to sub-critical dimension widths is selected to be sufficient that the portions of patterned photoresist at the critical dimension support the interleaved portions at below the critical dimension. When applied to the patterning of conductive gate material, the resulting device, in MOS technology, provides improved drive current by providing an effectively shorter channel length, for a given photolithography process.
REFERENCES:
patent: 5644121 (1997-07-01), Nakano et al.
patent: 6040118 (2000-03-01), Capodieci
patent: 6184041 (2001-02-01), Furukawa et al.
patent: 6218082 (2001-04-01), Yang
patent: 2002/0094614 (2002-07-01), Maeda et al
Mehrotra Manoj
Randall John N.
Rodder Mark S.
Brady III W. James
Diáz José R.
Eckert George
McLarty Peter K.
Telecky , Jr. Frederick J.
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