Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1998-10-30
2001-03-06
Meeks, Timothy (Department: 1762)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S431000, C438S787000, C438S790000, C427S255370
Reexamination Certificate
active
06197658
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming trench fill layers within trenches within substrates employed in microelectronics fabrication. More particularly, the present invention relates to methods for forming gap filling trench fill layers within trenches within substrates employed in microelectronics fabrication.
2. Description of the Related Art
In the art of microelectronics fabrication, integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes, capacitors and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by patterned and/or blanket dielectric layers.
As integrated circuit device technology has advanced and integrated circuit device dimensions have decreased, it has become increasingly common within advanced integrated circuits to employ electrical isolation methods such as shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods to form trench isolation regions nominally co-planar with adjoining active semiconductor regions of semiconductor substrates. Such trench isolation methods typically employ a chemical mechanical polish (CMP) planarizing method to provide a nominally planarized surface to a trench isolation region formed from a trench fill dielectric layer formed within a trench. Within the chemical mechanical polish (CMP) planarizig methods, means and materials are required to insure that when the desired degree of planarization is achieved the planarizing process is brought to completion without damage to underlying regions of the microelectronics fabrication.
Trench isolation regions nominally co-planar with active semiconductor regions within semiconductor substrates are desirable since they optimize, when subsequently forming patterned layers upon those nominally co-planar regions, the limited depth of focus typically obtained with advanced photoexposure tooling employed in the microelectronics fabrication art.
When forming within advanced integrated circuits trench isolation regions within isolation trenches, it has become common to employ as trench fill dielectric layers gap filling silicon oxide layers formed employing ozone assisted satmospheric pressure thermal chemical vapor deposition (SACVD) methods. Silicon oxide layers formed employing such methods are desirable since such silicon oxide layers typically possess the inherently superior gap filling characteristics desirable for trenches of limited dimensions typically encountered in advanced integrated circuit microelectronics fabrication.
While gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods are desirable as trench fill layers within trenches within advanced integrated circuit microelectronics fabrications, methods through which are formed such gap filling silicon oxide layers are not entirely without problems. Specifically, it is known in the art of integrated circuit microelectronics fabrication that gap filling silicon oxide layers formed employing ozone assisted subatmospheric pressure thermal chemical vapor deposition (SACVD) methods exhibit a surface sensitivity dependent upon the substrate layers upon which are formed those gap filling silicon oxide layers. In particular, when employing as substrate layers thermally grown silicon oxide layers formed within silicon semiconductor substrates, gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods exhibit inhibited formation rates in comparison with otherwise equivalent gap ffling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods upon substrate layers other than thermally grown silicon oxide layers. The gap filing silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods upon the thermally grown silicon oxide layers also typically exhibit inferior bulk quality (as determined by wet etch rates in dilute hydrofluoric acid) in comparison with otherwise equivalent gap filling silicon oxide layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods upon substrate layers other than thermally grown silicon oxide layers.
Inhibited formation rates within isolation trenches within semiconductor substrates of gap filling silicon oxide trench fill layers formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods are undesirable since there is then formed within those isolation trenches gap filling silicon oxide layers which are particularly susceptible to dishing when subsequently planarized employing chemical mechanical polish (CMP) planarizing methods.
The planarizing methods typically remove not only silicon oxide trench fill layer material but any other silicon oxide materials such as thermal silicon oxide, conformal silicon oxide, etc. Therefore, it is customary to interpose a non-reactive substance such as silicon nitride between the underlying layers and such gap filling silicon oxide trench fill layers to act as a barrier or stop layer to prevent further removal of material as a consequence of the planarizing process, thus adding cost and complexity to the microelectronics fabrication. Also, inferior bulk quality of such gap filling silicon oxide trench fill layers often compromises the dielectric properties of such gap filling silicon oxide trench fill layers. Finally, enhanced surface roughness of such gap filling silicon oxide trench fill layers is undesirable since enhanced surface roughness of such gap filling silicon oxide trench fill layers often provides gap filling silicon oxide trench fill layers of enhanced porosity.
It is thus towards the goal of forming within advanced integrated circuit microelectronics fabrications gap filling silicon oxide trench fill layers formed employing ozone assisted subatmospheric pressure thermal chemical vapor deposition (SACVD) methods with enhanced bulk quality while attenuating a surface sensitivity when forming those gap filling silicon oxide trench fill layers, that the present invention is generally directed.
Methods and materials through which silicon oxide layers may be formed with desirable properties within integrated circuit microelectronics fabrications are known in the art of integrated circuit microelectronics fabrication.
For example, Jang et al, in U.S. Pat. No. 5,731,241, disclose a method for protecting a trench fill silicon oxide layer from excessive etching during multiple etching steps when forming the trench fill silicon oxide layer. The method employs a sacrificial silicon oxide layer formed selectively, while employing a sub-atmospheric pressure chemical vapor deposition (SACVD) method, upon a silicon oxide trench fill layer within a trench within a silicon substrate, wherein the sacrificial silicon oxide layer has a greater differential etch rate over the trench fill region and functions as a sacrificial layer to protect the trench fill silicon oxide.
Further, Jang et al., in U.S. Pat. No. 5,726,090, disclose a method for enhancing gap filling characteristics of ozone assisted subatmospheric pressure thermal chemical vapor deposited (SACVD) silicon oxide dielectric layers formed upon thermal silicon oxide trench liner layers within semiconductor substrates within semiconductor integrated circuit microelectronics fabrications. The method employs an intermediate silicon oxide trench liner layer formed upon the thermal silicon oxide trench liner layer prior to forming the ozone assisted sub-atmospheric pressure thermal chemical vapor deposited (SACVD) silicon oxide dielectric layer over the thermal silicon oxide trench liner l
Ackerman Stephen B.
Meeks Timothy
Saile George O.
Stanton Stephen G.
Taiwan Semiconductor Manufacturing Company
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