Stud formation method optimizing insulator gap-fill and metal ho

Details Stud formation method optimizing insulator gap-fill and metal ho Stud formation method optimizing insulator gap-fill and metal ho

1987-08-17

1988-07-19

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156645, 156646, 156651, 156652, 156653, 156656, 156657, 1566591, 20419232, 357 49, 357 67, 437228, 437198, 437199, B44C 122, C03C 1500, C03C 2506, C23F 102

Patent

active

047583061

ABSTRACT:
A method of forming a conductive structure on a substrate by using both of the via-filling and stud-forming metallization techniques. A stud that is approximately one-half the thickness of the final stud is defined on a conductive layer. The stud-forming mask is left in place. Then the sidewalls of the mask are positively tapered, and an insulator layer is deposited on the substrate. The insulator is then etched to expose the stud forming mask, and the mask is removed. The sidewalls of the vias thus defined in the insulator layer are then positively tapered. By positively tapering both the stud mask prior to insulator deposition and the insulator via prior to metal deposition, insulator gap-fill and metal hole-fill problems are eliminated.

REFERENCES:
patent: 4307179 (1981-12-01), Chang et al.
patent: 4572765 (1986-02-01), Berry
patent: 4575402 (1986-03-01), Marcoux et al.
patent: 4595452 (1986-06-01), Landau et al.
patent: 4597826 (1986-07-01), Majima et al.

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