Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-11-01
2002-04-23
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S613000, C438S614000, C438S650000, C228S180220
Reexamination Certificate
active
06376352
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a known good die (KGD) carrier membrane and to a method of fabricating the membrane.
BRIEF DESCRIPTION OF THE PRIOR ART
At present, the known good die carrier industry is limited by the pad pitch and number of bumps that can be placed economically upon a single temporary test carrier used to manufacture KGD. A great deal of development work has been performed on this problem. It has been demonstrated that the use of a polymer membrane with plated bumps is a technology that could not be easily developed. The use of a conductive polymer that is screened upon the ceramic membrane is limited by the pitch constraints of the screening techniques which are pushed to the maximum at about 4 mils. This is insufficient to support the newer generation of semiconductor devices.
A further problem encountered is the cost associated with the procuring of membranes used to route the signals in the test carriers. The membranes include conductive paths to the test contactor from conductive bumps that interface with the die product. The cost of fabricating such membranes is presently not economically viable.
SUMMARY OF THE INVENTION
In accordance with the present invention, the problems inherent in the prior art are minimized and there is provided a bump technology that meets the pitch requirements of the evolving semiconductor products and which can be placed upon a low cost membrane with electrically conductive traces thereon that mirror the test carrier requirements. The technology for providing the bump is provided in the form of gold ball bond stud bumps. Stud bumps are capable of being produced to the tightest pitch that a gold ball bond can be placed on a semiconductor device. The stud bump has a fair degree of planarity within about 12 microns under present technology. This can be improved by coining the top of the stud bump with a hard metal surface. The stud bump is bonded to a low cost silicon or ceramic membrane which will fit into the KGD carrier. In order to obtain compliance and coplanarity upon the top of the stud bump for interface with the semiconductor device to be tested, the stud bump is coated with a solution of electrically conductive polymer. The electrically conductive polymer is the “cone” portion of the stud cone bump. The electrically conductive polymer over the stud bump provides the bump with the necessary compliance to conform to the surface of the semiconductor die to be tested. The electrically conductive polymer is filled with a material that forms a jagged edge on top of the cone that breaks the oxide present on the die bond pads. This material can be electrically conductive or non-conductive, so long as the bump is electrically conductive. Silver flakes have been found to work well as the filling material. The electrically conductive polymer develops coplanarity across the surface of the test membrane the first time the device is loaded into the carrier. The electrically conductive polymers used are ones that are readily available and are well known. The stud bumping on the membranes is performed with a standard gold ball bonder. The cone is applied by dipping the tips of the stud bumps into a bath of the electrically conductive polymer to provide a thin film of the electrically conductive polymer over the cone.
A principal feature of this invention lies in the utilization of proven prior art technologies in the flip chip bonding, stud bumping and polymer interconnection fields. These technologies, when used for KGD application, are unique both alone as well as in the combination.
Advantages of the above described improvement are lower carrier membrane production costs relative to the prior art and greater ease of manufacture.
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Lin, J-K. et al, “Conductive Polymer Bump Interconnects”, Proceedings, Electronic Components and Technology conference, p 1059 (1996).
Arnold Richard W.
Beardain Weldon
Forster James A.
Wilson Lester L.
Bowers Charles
Brady III Wade James
Sarkar Asok Kumar
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