Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-06-30
2004-02-17
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S726000
Reexamination Certificate
active
06694454
ABSTRACT:
BACKGROUND OF THE INVENTION
Given the increasing complexity and density of current integrated circuit logic chips, the need to test the operation of logic in a reliable and efficient manner has become acute. One such test methodology is the so-called “level-sensitive scan design,” or LSSD. Briefly in LSSD testing a chain of shift register latches (SRLs) or flip-flops are coupled to the inputs and outputs of the internal logic under test. The test is scanned serially into an input chain of shift register latches. When the input shift register is full, the data propgates through the logic under test and is written into a second chain of SRLs or flip-flops. The acquired data is then scanned serially out and compared to the expected data. The LSSD test indicates that the logic is not functioning properly when the acquired data does not match the expected data. Given a list of failing tests and the latches found to contain incorrect values, a diagnostic fault simulator can generally produce a list of potential defects which could have caused the fails observed at the tester. However, in order to obtain tractable run times, diagnostic simulators typically assume that all scan chains on the chip are performing correctly, and bypass the explicit simulation of the scanning operations. For this reason, standard diagnostic simulation techniques are ineffective for diagnosing faults in scan chain circuitry.
Failures that cause logic to malfunction at desired clock rates are referred to as delay faults or AC faults. These delay faults are typically due to random variations in process parameters that may cause device and/or wiring propagation delays to exceed specified limits. Tests for delay employ LSSD and are typically structured to provoke a 0-to-1 transition at the site of the fault to test for a slow-to-rise fault and normally structured to provoke a 1-to-0 transition to test for a slow-to-fall fault. Reference is made to commonly-assigned U.S. Pat. No. 5,642,362, entitled “Scan-Based Delay Tests Having Enhanced Test Vector Pattern Generation,” issued on Jun. 24, 1997 to Savir for further information. As such, delay tests for logic circuits differ from static, stuck fault tests in that they characterize the dynamic properties of the circuit such as propagation delay.
One problem with using LSSD is that a greater and greater portion of the logic circuit area is taken up by the scan chains. Thus the chances of a failure appearing in the scan chain are becoming higher and higher. However, since normal diagnostic simulation techniques are not accurate for chips with defective scan chains, an increasing number of chips which require physical failure analysis can not be diagnosed using traditional methods. Since normal diagnostic simulation techniques are not accurate for chips with defective scan chains, however, an increasing number of chips which require physical failure analysis can not be diagnosed using traditional methods. There are several approaches proposed to solve stuck fault problems in defective scan chains. Examples of some approaches are “Scan Chain Diagnosis using IDDQ Current Measurement,” by Hirase, et al., Proc. IEEE International Test Conference, page 153-157, February 1999, “Scan Chain Fault Diagnosis with Fault Dictionaries,” by Geetani Edrisooriya, IEEE VLSI Test Symposium, February 1995, and “On Diagnosis of Faults in a Scan-Chain, by Sandip Kundu, IEEE VLSI Test Symposium, March 1993.
The problem with these approaches is they do not diagnose dynamic or transient faults or are manual in their search techniques. One proposed method to reach such faults is “An Efficient Scheme to Diagnose Scan Chains,” by Sridhar Narayanan and Ashutosh Das, Proc. International Test Conference, pages 704-713, July 1997. The main idea of that approach is to add circuitry to a scan flop to enable its scan-out port to be either set or reset.
SUMMARY OF INVENTION
What is needed is a software technique that quickly and accurately diagnoses the failing latches in a defective scan chain, including those due to dynamic or transition defects. What the inventors have done is invent such a technique that is useful over a wide range of defect types and fault models and requires no special hardware or pattern generation.
To achieve the benefits of localizing scan chain defects, the inventors have created a diagnostic method called the High-Accuracy Flush-and-Scan Software Diagnostic. The method determines the defective latch by repeatedly simulating different loads (or initializations) until the simulation results match those from the tester.
More specifically the method for diagnosing faults in scan chains involves examining repeating patterns in the scan test to determine the type of fault, creating a symptom signature load for each fault based on the repeating patterns for each type of fault, running a simulation using the symptom signature at the assumed fault position, and comparing the simulated result with the actual scan test result to see if the fault position was determined.
In order to assist in the search of the fault position a search approach is used to determine the quality of the match at the assumed fault position.
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International Business Machines - Corporation
Iqbal Nadeem
Kotulak Richard M.
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