Structures with increased photo-alignment margins

Details Structures with increased photo-alignment margins Structures with increased photo-alignment margins

2006-07-31

2011-10-04

Ngo, Ngan (Department: 2893)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S791000, C438S736000, C438S942000, C438S401000, C430S005000, C257SE21023, C257SE21038, C257SE21039, C257SE21235, C257SE21240

Reexamination Certificate

active

08030222

ABSTRACT:
Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.

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