Structures for and method of silicide formation on memory...

Details Structures for and method of silicide formation on memory... Structures for and method of silicide formation on memory...

2009-03-13

2011-12-13

Vu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S142000, C257SE21691

Reexamination Certificate

active

08076708

ABSTRACT:
A memory device and peripheral circuitry on a substrate are described, made by a process that includes forming a charge trapping structure having a first thickness over a first area. A first gate dielectric layer having a second thickness is formed for low-voltage transistors. A second gate dielectric layer having a third thickness, greater than the second thickness, is formed for high-voltage transistors. Polysilicon is deposited and patterned to define word lines and transistor gates. The thickness of the second gate dielectric layer in regions adjacent the gates, and over a source and drain regions, is reduced to a thickness that is close to that of the second thickness.

REFERENCES:
patent: 6136636 (2000-10-01), Wu et al.
patent: 6316293 (2001-11-01), Fang
patent: 6461906 (2002-10-01), Lung
patent: 6566194 (2003-05-01), Ramsbey et al.

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