Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2006-01-17
2009-11-03
Tran, Minh-Loan T (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S127000, C257S170000, C257S409000, C257S484000, C257S605000, C257SE29012, C257SE29013
Reexamination Certificate
active
07612371
ABSTRACT:
The present invention addresses detection of charge-induced defects through test structures that can be easily incorporated on a wafer to detect charge-induced damage in the back-end-of-line processing of a semiconductor processing line. A test macro is designed to induce an arc from a charge accumulating antenna structure to another charge accumulating antenna structure across parallel plate electrodes. When an arc of a predetermined sufficient strength is present, the macro will experience a voltage breakdown that is measurable as a short. The parallel plate electrodes may both be at the floating potential of the microchip to monitor CMP-induced or lithographic-induced charge failure mechanisms, or have one electrode electrically connected to a ground potential structure to capture charge induced damage, hence having the capability to differentiate between the two.
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Ahsan Ishtiaq
Bunke Christine M.
Greco Stephen E.
Cai Yuanmin
DeLio & Peterson LLC
International Business Machines - Corporation
Lopez Fei Fei Yeung
Nowak Kelly M.
LandOfFree
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