Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-12-30
2004-08-17
Nhu, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S288000
Reexamination Certificate
active
06777734
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a static random access memory (SRAM) having an asymmetric silicide layer and a method for manufacturing the same, and more particularly, to a structure of a static random access memory (SRAM) having an asymmetric silicide layer and a method for manufacturing the same which are capable of increasing the cell ratio without changing the size of an actuating transistor or an actuating transistor to form the SRAM.
2. Description of the Related Art
Generally, although an SRAM is inferior in memory capacity to a dynamic random access memory (DRAM), it has been widely used in the memory field such as a cash memory of a computer which requires high speed operation since it operates.
Typically, the SRAM cell is composed of a flip flop circuit provided with a pair of actuating transistors and a pair of actuating transistors, so that memory information is conserved by the voltage difference between an input and an output terminal of the flip flop, i.e., electrical charges accumulated in a cell node. Also, since the electrical charges are constantly compensated from the power source Vcc through a p-channel metal oxide semiconductor (PMOS) transistor as an actuating transistor or a load resistor, the SDRAM does not require a refresh function, as does a DRAM.
FIG. 1
is a view showing the circuit of a conventional SRAM cell. Referring to
FIG. 1
, the circuit of a SRAM cell includes a pair of actuating transistors
10
provided with a PMOS transistor
12
and an n-channel metal oxide semiconductor (NMOS) transistor
14
being connected to the terminals of a power supply successively and a pair of actuating transistors
20
connecting its source to a gate electrode of the actuating transistor
10
alternately. Here, the source of the transfer transistor
20
is crossed at a common node of the PMOS transistor
12
and the NMOS transistor
14
of the actuating transistors
10
. The terminals of the power source are connected to a drain of the PMOS transistor
12
of the actuating transistors
10
and a ground terminal is connected to the source of the NMOS transistor
14
. A word line (WL) is connected to gate electrodes of the actuating transistors
20
and bit lines BL, /BL are connected to the source.
FIGS. 2
a
to
2
c
are cross-sectional views illustrating a method for manufacturing an SPAM in accordance with a prior art. Referring to
FIGS. 2
a
to
2
c
, a conventional method for manufacturing an SRAM will now be described. Here, methods for manufacturing a PMOS transistor
12
as an actuating transistor
10
of an SRAM cell and an NMOS transistor as a transfer transistor
20
as shown in
FIG. 1
are explained for simplicity.
As shown in
FIG. 2
a
, a device isolation layer
2
is formed on a semiconductor substrate
1
and an n-well
3
and a p-well
4
are formed in the semiconductor substrate
1
, respectively. A gate insulating layer
5
and gate electrodes
6
of the transfer transistors
20
and the actuating transistor, e.g., the PMOS transistor
12
, are sequentially formed on top of the n-well
3
and the p-well
4
of the semiconductor substrate
1
. Also, spacers
7
are formed on a side wall of the gate electrodes
6
, a p+ source/drain
8
of the actuating transistor is formed on the n-well
3
and n+ source/drain
9
of the transfer transistor
20
is formed on the p-well
4
. Here, each of the source/drains
8
,
9
employs a lightly doped drain (LDD) structure.
Subsequently, as shown in
FIG. 2
b
, a silicide layer
11
is formed on a top of the actuating transistor
12
and the gate electrodes
6
of the transfer transistor
20
and a surface of the source/drain electrodes
8
,
9
by performing a salicide process.
Then, as shown in
FIG. 2
c
, an interlayer insulating layer
13
is formed on an entire surface of the resultant structure formed with the silicide layer
11
, a contact hole is formed in the interlayer insulating layer
13
and contact electrodes
15
are formed with a conductive layer to connect the actuating transistor
12
and the source/drain of the transfer transistor
20
.
After the constructed SRAM cell applies a voltage opposite to each other to the bit lines BL, /BL to store data in the cell, the transfer transistor
20
is turned on by applying the driving power to the word line and the voltage of the bit lines BL, /BL is stored at a common node of the PMOS and the NMOS of the actuating transistor
12
based on the status of the transfer transistor. After the bit lines BL, /BL are precharged with the same voltage to read the data stored at the SRAM cell, the bit lines BL, /BL change into electrical potentials different form each other due the a valued stored at the actuating transistor
10
by applying the driving power to the word line. This result is sensed by a sense amplifier and the difference between the potentials is amplified to thereby read the data.
Conventionally, there is a major parameter called a cell ratio to secure a stable data maintaining function and a data stability during a data access. If the precharged transfer transistor
20
is turned on to read the data of the SRAM cell, a potential of one of the bit lines BL, /BL is changed, whereby the stability of the data is dependent on the force of driving a current of the actuating transistor
10
. To understand this effect, the ratio between the current driving forces of the actuating transistor/transfer transistor is defined as a cell ratio, and preferably is approximately larger than two.
Whereas, in the SRAM cell, there is a method to increase a width/length ratio of the transistor so as to increase the cell ratio in a given electron mobility and gate capacitance. A method to reduce the length for the same width has a limit due to the fixation of a minimum value to supply a given processor, therefore, a method to increase the width for the same length has been widely used. However, it causes an increase in the area of the SRAM cell, thereby making a high integration of the semiconductor device difficult.
SUMMARY OF THE INVENTION
It is a major object of the present invention to solve the above mentioned problems of the prior art and to provide a structure of a static random access memory (SRAM) having an asymmetric silicide layer which is capable of increasing the cell ratio without increasing the size of an SRAM cell by reducing the current driving force of a transfer transistor in comparison with that of the actuating transistor, this is achieved by increasing surface resistance of the transfer transistor by not forming a silicide thereon and decreasing surface resistance of the actuating transistor by forming a silicide thereon.
It is another object of the present invention to provide to a method for manufacturing a static random access memory (SRAM) having an asymmetric silicide layer which is capable of increasing a cell ratio without increasing the size of an SRAM cell by reducing the current driving force of a transfer transistor in comparison with that of the actuating transistor, this is achieved by increasing the surface resistance of the transfer transistor by not forming a silicide thereon and decreasing surface resistance of the actuating transistor by forming a silicide thereon.
In accordance with one aspect of the present invention, there is provided a structure of a static random access memory (SRAM) having an asymmetric silicide layer, wherein the SRAM is provided with transfer transistors and actuating transistors, the structure including: a semiconductor substrate provided with a substructure of a predetermined configuration; a gate insulating layer and gate electrodes of the transfer transistors and the actuating transistors formed on the semiconductor substrate spaced at a predetermined distance; a spacer formed on side walls of the gate electrodes of the transfer transistors and the actuating transistors, respectively; source/drain electrodes of the transfer transistors and the actuating transistors implanted into a portion of the semiconductor
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
Nhu David
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