Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2007-10-16
2007-10-16
Menz, Douglas M. (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S676000, C257S700000, C257S723000
Reexamination Certificate
active
10614928
ABSTRACT:
A new method and package for the mounting of semiconductor devices. A silicon substrate serves as the device supporting medium, active semiconductor devices have been created in or on the surface of the silicon substrate. A solder plate is created over the surface of the substrate that aligns with the metal points of contact in the surface of the substrate. Semiconductor devices that have been provided with solder bumps or pin-grid arrays are connected to the solder plate. Underfill is applied to the connected semiconductor devices, the devices are covered with a layer of dielectric that is planarized. Inter-device vias are created in the layer of dielectric down to the surface of the substrate, re-routing interconnect lines are formed on the surface of the dielectric. Contact balls are connected to the re-routing lines after which the semiconductor devices that have been mounted above the silicon substrate are separated by die sawing. At this time, the separated semiconductor devices have two levels of ball interconnects, this can be further extended to for instance three levels of balls interconnect be connecting the second level of ball interconnect to a first surface of a Printed Circuit Board (PCB) while additional contact balls are connected to a second surface of this PCB.
REFERENCES:
patent: 5081563 (1992-01-01), Feng et al.
patent: 5422435 (1995-06-01), Takiar et al.
patent: 5608262 (1997-03-01), Degani et al.
patent: 5811351 (1998-09-01), Kawakita et al.
patent: 5870289 (1999-02-01), Tokuda et al.
patent: 5952725 (1999-09-01), Ball
patent: 5994166 (1999-11-01), Akram et al.
patent: 6051878 (2000-04-01), Akram et al.
patent: 6157080 (2000-12-01), Tamaki et al.
patent: 6165815 (2000-12-01), Ball
patent: 6168969 (2001-01-01), Farnworth
patent: 6222265 (2001-04-01), Akram et al.
patent: 6265766 (2001-07-01), Moden
patent: 6340846 (2002-01-01), LoBianco et al.
patent: 6365499 (2002-04-01), Nakamura et al.
patent: 6413798 (2002-07-01), Asada
patent: 6451624 (2002-09-01), Farnworth et al.
patent: 6489676 (2002-12-01), Taniguchi et al.
Article, published as part of the 2000 Electronic Components and Tech. Conf. of May 21, 2000-May 24, 2000, by Jean Dufresne, “Hybrid Assembly Technology for Flip-Chip-on-Chip (FCOC) Using PBGA Laminate Assembly”, Ref. #0-7803-5908-9/00, IEEE.
Ackerman Stephen B.
Megica Corporation
Menz Douglas M.
Pike Rosemary L. S.
Saile Ackerman LLC
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