Structure of high performance combo chip and processing method

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip

Reexamination Certificate

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C257S676000

Reexamination Certificate

active

07960842

ABSTRACT:
A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump.

REFERENCES:
patent: 3668484 (1972-06-01), Greig
patent: 4825276 (1989-04-01), Kobayashi
patent: 5081563 (1992-01-01), Feng et al.
patent: 5083187 (1992-01-01), Lamson
patent: 5239447 (1993-08-01), Cotues
patent: 5422435 (1995-06-01), Takiar et al.
patent: 5468984 (1995-11-01), Efland
patent: 5534465 (1996-07-01), Frye
patent: 5608262 (1997-03-01), Degani et al.
patent: 5659952 (1997-08-01), Kovac et al.
patent: 5688716 (1997-11-01), DiStefano et al.
patent: 5780925 (1998-07-01), Cipolla et al.
patent: 5811351 (1998-09-01), Kawakita et al.
patent: 5866949 (1999-02-01), Schueller
patent: 5870289 (1999-02-01), Tokuda et al.
patent: 5874781 (1999-02-01), Fogal
patent: 5915170 (1999-06-01), Raab et al.
patent: 5952725 (1999-09-01), Ball
patent: 5983492 (1999-11-01), Fjelstad
patent: 5989939 (1999-11-01), Fjelstad
patent: 5994166 (1999-11-01), Akram et al.
patent: 6012224 (2000-01-01), DiStefano et al.
patent: 6020220 (2000-02-01), Gilleo et al.
patent: 6051878 (2000-04-01), Akram et al.
patent: 6054337 (2000-04-01), Solberg
patent: 6087722 (2000-07-01), Lee
patent: 6121682 (2000-09-01), Kim
patent: 6133639 (2000-10-01), Kovac et al.
patent: 6147401 (2000-11-01), Solberg
patent: 6157080 (2000-12-01), Tamaki et al.
patent: 6165815 (2000-12-01), Ball
patent: 6168969 (2001-01-01), Farnworth
patent: 6177731 (2001-01-01), Ishida
patent: 6180426 (2001-01-01), Lin
patent: 6207467 (2001-03-01), Vaiyapuri
patent: 6211572 (2001-04-01), Fjelstad et al.
patent: 6222265 (2001-04-01), Akram et al.
patent: 6229711 (2001-05-01), Yoneda
patent: 6236109 (2001-05-01), Hsuan
patent: 6239367 (2001-05-01), Hsuan
patent: 6252301 (2001-06-01), Gilleo et al.
patent: 6265766 (2001-07-01), Moden
patent: 6274937 (2001-08-01), Ahn
patent: 6284563 (2001-09-01), Fjelstad
patent: 6294406 (2001-09-01), Bertin
patent: 6300254 (2001-10-01), Raab
patent: 6313528 (2001-11-01), Solberg
patent: 6340846 (2002-01-01), LoBianco et al.
patent: 6359335 (2002-03-01), Distefano et al.
patent: 6365499 (2002-04-01), Nakamura et al.
patent: 6413798 (2002-07-01), Asada
patent: 6451624 (2002-09-01), Farnworth et al.
patent: 6465878 (2002-10-01), Fjelstad et al.
patent: 6489676 (2002-12-01), Taniguchi et al.
patent: 6504227 (2003-01-01), Matsuo
patent: 6538331 (2003-03-01), Masuda
patent: 6541847 (2003-04-01), Hofstee
patent: 6558978 (2003-05-01), McCormick
patent: 6586266 (2003-07-01), Lin
patent: 6613606 (2003-09-01), Lee
patent: 6642610 (2003-11-01), Park
patent: 6653563 (2003-11-01), Bohr
patent: 6707149 (2004-03-01), Smith
patent: 6707159 (2004-03-01), Kumamoto
patent: 6716671 (2004-04-01), Warner et al.
patent: 6723584 (2004-04-01), Kovac et al.
patent: 6756664 (2004-06-01), Yang
patent: 6762122 (2004-07-01), Mis
patent: 6765299 (2004-07-01), Takahashi et al.
patent: 6774475 (2004-08-01), Blackshear
patent: 6791178 (2004-09-01), Yamaguchi
patent: 6847101 (2005-01-01), Fjelstad et al.
patent: 6847107 (2005-01-01), Fjelstad et al.
patent: 6870272 (2005-03-01), Kovac et al.
patent: 6963136 (2005-11-01), Shinozaki
patent: 6977435 (2005-12-01), Kim
patent: 7045899 (2006-05-01), Yamane
patent: 7074050 (2006-07-01), Bartley
patent: 7084660 (2006-08-01), Ackaret
patent: 7112879 (2006-09-01), Fjelstad et al.
patent: 7152311 (2006-12-01), Beroz et al.
patent: 7247932 (2007-07-01), Lin
patent: 7282804 (2007-10-01), Lee
patent: 7408260 (2008-08-01), Fjelstad et al.
patent: 7505284 (2009-03-01), Offrein
patent: 7517778 (2009-04-01), Lee et al.
patent: 2001/0007375 (2001-07-01), Fjelstad et al.
patent: 2001/0040290 (2001-11-01), Sakurai
patent: 2002/0100961 (2002-08-01), Fjelstad et al.
patent: 2002/0115236 (2002-08-01), Fjelstad et al.
patent: 2002/0195685 (2002-12-01), Fjelstad et al.
patent: 2004/0227225 (2004-11-01), Fjelstad et al.
patent: 2006/0237836 (2006-10-01), Fjelstad et al.
patent: 2006/0261476 (2006-11-01), Fjelstad et al.
patent: 2008/0070345 (2008-03-01), Lin et al.
patent: 2008/0070346 (2008-03-01), Lin et al.
patent: 2008/0284037 (2008-11-01), Andry
patent: 2009/0057901 (2009-03-01), Lin et al.
patent: 2009/0065937 (2009-03-01), Lin et al.
patent: 337036 (1998-07-01), None
patent: 369690 (1999-09-01), None
patent: 415056 (2000-12-01), None
patent: 432562 (2001-05-01), None
patent: 445599 (2001-07-01), None
Dufresne, J. et al. “Hybrid Assembly Technology for Flip-Chip-on-Chip (FCOC) Using PBGA Laminate Assembly,” pp. 541-548, IEEE Electronic Components and Technology Conference, May 21-24, 2000.
Mistry, K. et al. “A 45nm Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging,” IEEE International Electron Devices Meeting (2007) pp. 247-250.
Edelstein, D.C., “Advantages of Copper Interconnects,” Proceedings of the 12th International IEEE VLSI Multilevel Interconnection Conference (1995) pp. 301-307.
Theng, C. et al. “An Automated Tool Deployment for ESD (Electro-Static-Discharge) Correct-by-Construction Strategy in 90 nm Process,” IEEE International Conference on Semiconductor Electronics (2004) pp. 61-67.
Gao, X. et al. “An improved electrostatic discharge protection structure for reducing triggering voltage and parasitic capacitance,” Solid-State Electronics, 27 (2003), pp. 1105-1110.
Yeoh, A. et al. “Copper Die Bumps (First Level Interconnect) and Low-K Dielectrics in 65nm High Volume Manufacturing,” Electronic Components and Technology Conference (2006) pp. 1611-1615.
Hu, C-K. et al. “Copper-Polyimide Wiring Technology for VLSI Circuits,” Materials Research Society Symposium Proceedings VLSI V (1990) pp. 369-373.
Roesch, W. et al. “Cycling copper flip chip interconnects,” Microelectronics Reliability, 44 (2004) pp. 1047-1054.
Lee, Y-H. et al. “Effect of ESD Layout on the Assembly Yield and Reliability,” International Electron Devices Meeting (2006) pp. 1-4.
Yeoh, T-S. “ESD Effects on Power Supply Clamps,” Proceedings of the 6th International Sympoisum on Physical & Failure Analysis of Integrated Circuits (1997) pp. 121-124.
Edelstein, D. et al. “Full Copper Wiring in a Sub-0.25 pm CMOS ULSI Technology,” Technical Digest IEEE International Electron Devices Meeting (1997) pp. 773-776.
Venkatesan, S. et al. “A High Performance 1.8V, 0.20 pm CMOS Technology with Copper Metallization,” Technical Digest IEEE International Electron Devices Meeting (1997) pp. 769-772.
Jenei, S. et al. “High Q Inductor Add-on Module in Thick Cu/SiLK™ single damascene,” Proceedings from the IEEE International Interconnect Technology Conference (2001) pp. 107-109.
Groves, R. et al. “High Q Inductors in a SiGe BiCMOS Process Utilizing a Thick Metal Process Add-on Module,” Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (1999) pp. 149-152.
Sakran, N. et al. “The Implementation of the 65nm Dual-Core 64b Merom Processor,” IEEE International Solid-State Circuits Conference, Session 5, Microprocessors, 5.6 (2007) pp. 106-107, p. 590.
Kumar, R. et al. “A Family of 45nm IA Processors,” IEEE International Solid-State Circuits Conference, Session 3, Microprocessor Technologies, 3.2 (2009) pp. 58-59.
Bohr, M. “The New Era of Scaling in an SoC World,” International Solid-State Circuits Conference (2009) Presentation Slides 1-66.
Bohr, M. “The New Era of Scaling in an SoC World,” International Solid-State Circuits Conference (2009) pp. 23-28.
Ingerly, D. et al. “Low-K Interconnect Stack with Thick Metal 9 Redistribution Layer and Cu Die Bump for 45nm High V

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