Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-05-09
2003-11-04
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S406000
Reexamination Certificate
active
06642570
ABSTRACT:
The present invention relates to a semiconductor device, and more specifically, to a method of fabricating flash memories and the structure of the same.
BACKGROUND OF THE INVENTION
Various nonvolatile memories have been disclosed in the prior art. For example, Mitchellx has proposed EPROMs with self-aligned planar array cell. In this technique, buried diffusion self-aligned to the floating gate avalanche injection MOS transistors are used for the bit lines. Cross point array technology has been disclosed. The self-aligned source and drain will allow this device to be optimized even further for programming speed. See A. T. Mitchellx, “A New Self-Aligned Planar Cell for Ultra High Density EPROMs”, IEDM, Tech. pp. 548-553, 1987”.
Flash memory is one of the segments of nonvolatile memory devices. The device includes a floating gate to storage charges and an element for electrically placing charge on and removing the charges from the floating gate. One of the applications of flash memory is BIOS for computer. Typically, the high-density nonvolatile memories can be applied as the mass storage of portable handy terminals, solid state camera and PC cards. That is because that the nonvolatile memories exhibit many advantages, such as a fast access time, low power dissipation, and robustness. Bergemont proposed another cell array for portable computing and telecommunications application, which can be seen in Bergmont et al., “Low Voltage NVG™: A New High Performance 3 V/5 V Flash Technology for Portable Computing and Telecommunications Applications”, IEEE Trans. Electron Devices, vol. ED-43, p. 1510, 1996. This cell structure is introduced for low voltage NOR Virtual Ground (NVG) flash memory having fast access time. In the flash array schematic, field oxides (FOX) are formed between cells such that a poly extension on FOX of each cell provides adequate gate coupling ratio. Bergmont also mentioned that the portable telecommunications and computing have become a major driving force in the field of integrated circuits. In the article, the access time is one of the key concerns for low voltage read operation. The NVG array uses select devices to achieve a fast access time by reducing the pre-charge time to that of a single segment rather than the full bit-line.
The formation of nonvolatile memories toward the trends of low supply power and fast access, because these requirements are necessary for the application of the mobile computing system. Flash memory needs the charges to be hold in the floating gate for a long periods of time. Therefore, the dielectric that is used for insulating the floating gate needs to be high performance. At present, the low voltage flash memory is applied with a voltage of about 3V or 5V during charging or discharging the floating gate. As known in the art, tunneling is a basic technology in charging or discharging. In order to attain high tunneling efficiency, the thickness of the dielectric between the floating gate and substrate have to be scaled down due to the supply voltage is reduced.
U.S. Pat. No. 6,180,459 to Sheu, entitled “Method for fabricating a flash memory with shallow trench isolation”, filed on Jan. 8, 1999. The prior art disclosed a method for fabricating a flash memory comprising forming a shallow trench isolation (STI) structure is also formed in the method. A further U.S. Pat. No. 6,172,395 to Chen, et al., entitled “Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby” and assigned to Taiwan Semiconductor Manufacturing Company (Hsin-Chu, TW).
A further prior article can be seen in U.S. Pat. No. 6,171,909 to Ding, et al., entitled “Method for forming a stacked gate” and assigned to United Semiconductor Corp. (Hsinchu, TW) and the prior art is filed on Apr. 16, 1999. The method includes forming a first dielectric layer, a conductive layer and a silicon nitride layer sequentially over a substrate. A photoresist pattern is formed over the silicon nitride layer. The silicon nitride layer, conductive layer, first dielectric layer and substrate are etched by using the photoresist pattern as an etching mask until forming a plurality of trenches in the substrate. An insulating layer is formed over the substrate. A conductive spacer is formed on the sidewalls of the conductive layer and silicon nitride layer, wherein the conductive spacer and conductive layer serve as a first gate conductive layer. The silicon nitride layer is removed. A second dielectric layer and a second gate conductive layer are formed over the substrate. The second gate conductive layer, second dielectric layer and first gate conductive layer are patterned to form a control gate, a patterned dielectric layer and a floating gate, respectively.
SUMMARY OF THE INVENTION
The object of the present invention is to form a self-aligned floating gate with higher coupling ratio.
The further object is to form the floating gate and trench without switching the chamber.
The yet object of the present invention is to form the floating gate and trench, simultaneously.
The present invention comprises forming a tunneling dielectric layer on the substrate and a first conductive layer, such as a first polysilicon layer, on the tunneling dielectric layer. Then, patterning the first conductive layer, the tunneling dielectric layer and the substrate to form trenches therein before a gap-filling material is refilled into the trenches and over the substrate. A portion of the gap-filling material is removed to form trench isolations. A portion of the trench isolation is etched to form slots between the etched first conductive layer. Next, a second conductive layer is formed over a surface of the slots and the etched first conductive layer. The second conductive layer is etched, thereby forming sidewall spacers on the slot where the spacers are not higher than the top surface of the first conductive layer. The next step is to form a second dielectric layer on the trench isolation, the sidewall spacers and the first conductive layer; and forming a third conductive layer on the second dielectric layer to act as a control gate.
The flash memory structure includes a substrate having trenches formed therein, a first dielectric layer and a first conductive layer are stacked on the substrate. Isolations are formed in the trenches and protruding over the surface of the substrate, wherein the first conductive layer is also protruded over the isolations. A second conductive layer is lying the surface of the first conductive layer and a second dielectric layer formed thereon. A third conductive layer is formed on the second dielectric layer. The floating gate is consisted of first conductive layer and the second conductive layer.
REFERENCES:
patent: 5108939 (1992-04-01), Manley et al.
patent: 5915176 (1999-06-01), Lim
patent: 6049114 (2000-04-01), Maiti et al.
patent: 6171909 (2001-01-01), Ding et al.
patent: 6228716 (2001-05-01), Wanlass
patent: 6235589 (2001-05-01), Meguro
patent: 6274434 (2001-08-01), Koido et al.
Cheng Clement
Nelms David
Nguyen Thinh T.
Vanguard International Semiconductor Corp.
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