Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-30
2004-05-04
Fahmy, Jr., Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S296000, C257S550000, C438S257000
Reexamination Certificate
active
06730959
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a structure of a non-volatile memory device and a method for fabricating the same. More particularly, the present invention relates to a structure of a flash memory device method and a method for fabricating thereof.
2. Description of Related Art
A flash memory device provides the property of multiple entries, retrievals and erasures of data. Moreover, the stored information is retained even electrical power is interrupted. As a result, the non-volatile memory device is widely used in personal computers and electronic systems.
A typical flash memory device employs doped polysilicon for the formation of the floating gate and the control gate. During the programming and the erasing of this type of flash memory device, an appropriate voltage is applied to the source region, the drain region and the control gate to inject electrons into and to eject electrons from the polysilicon floating gate.
In general, electron injection for a flash memory device includes the channel hot-electron injection (CHEI) model and the Fowler-Nordheim Tunneling model. The programming and the erasing of a device are accomplished by either the injection or ejection of electrons.
Referring to
FIG. 1
,
FIG. 1
is a schematic diagram, illustrating the structure of a conventional stacked gate flash memory (U.S. Pat. No. 6214668). A conventional flash memory device is formed with a p-type substrate
100
, a deep N-type well region
102
, a P-type well region
104
, a stacked gate structure
106
, a source region
108
, a drain region
110
, a spacer
112
, an inter-layer dielectric layer
114
, a contact
116
and a conductive line
118
. The stacked gate structure
106
comprises a tunnel oxide layer
120
, a floating gate
122
, a gate dielectric layer
124
, a control gate
126
and a gate cap layer
128
. The deep N-type well
102
is located in the P-type substrate
100
. The stacked gate structure
106
is disposed the substrate
100
. The source region
108
and the drain region
110
are located beside the sides of the stacked gate structure
106
in the P-type substrate
100
. The spacer
112
is disposed on the sidewall of the stacked gate structure
106
. The P-type well region
104
is located in the N-type deep well region
102
, extending from the drain region
110
to substrate
100
underneath the stacked gate structure
106
. The interlayer dielectric layer
114
is disposed on the P-type substrate
100
. The contact
116
penetrates through the inter-layer dielectric layer
114
and the substrate
100
, short-circuiting the P-type well region
104
and the drain region
110
. The conductive line
118
is disposed above the interlayer dielectric layer
114
and electrically connected with the contact
116
.
During the fabrication of the flash memory device illustrated in
FIG. 1
, the P-type well region
104
is formed by forming a mask layer (not shown) on the entire P-type substrate
100
subsequent to the formation of the stacked gate structure
106
. This mask layer exposes a pre-determined region for forming the drain region. A tilt angle (0 degrees to 180 degrees) ion implantation process is then conducted to implant dopants to the deepN-type well region
102
in the P-type substrate
100
near the drain region on one side of the stacked gate structure
100
, using the stacked gate structure
106
and the mask layer as a mask. A drive-in process is then performed to extend the P-type well region
104
to the substrate
100
under the stacked gate structure
106
.
During the formation of the stacked gate structure, the silicon oxide etching rate is normally increased to completely remove the grid-shaped gate dielectric layer in order to prevent the gate dielectric layer debris remaining on the sidewall of the floating gate. The field oxide layer, not covered by the floating gate layer, is then over-etched to form a trench. Consequently, dopants that are implanted during the tilt angle ion implantation process (30 to 50 electronic volts of implantation energy) for the formation of the P-type well region
104
would penetrate through the field oxide layer, inducing a current leakage of the memory cell at the side of the drain region. Further, an ineffective isolation between the bit lines is resulted.
Additionally, to form the local P-well region, the subsequent dopant drive-in process is conducted under a temperature of 900 degrees Celsius and an oxygen gas ambient. The tunnel oxide layer along the edge of the floating gate
122
and the gate dielectric layer
124
(silicon oxide/silicon nitride/silicon oxide) would become thicker.
Further, the diffusion of the P-well driving-in is difficult to control. The efficiency and the yield of the device are adversely affected.
Further, the source regions of the flash memory devices is connected together through the deep N-type well region to form a source line. Since the resistance of a deep N-type well region is higher, the operational speed is affected. In order to increase the operational speed, a source line pickup is conventionally formed at every
16
memory cells in the active region, in other words,
16
bit lines, to lower the resistance of the deep N-type well region (source line). However, forming a source line pickup in the active region would lower the ration of the memory cell array. The integration of the device thereby can not be increased.
Further, during the formation of the contact
116
, the interlayer dielectric layer
114
and the P-type substrate
100
are etched to form a contact that penetrates through the interlayer dielectric layer
114
and the drain region
110
. The aspect ratio of the contact is thus very high. Moreover, two different materials (silicon oxide and silicon) are etched. Controlling the depth of the contact is thus very difficult. The difficulty of the manufacturing process is thereby increased. Also, during the back-end processing, the contact of the memory cell region and the contact of the periphery circuit region need to be separated. The back-end processing thus becomes more complicated.
SUMMARY OF INVENTION
Accordingly, the present invention provides a structure of a flash memory device and a fabrication method for the same, wherein forming an additional source line pickup is obviated while the reliability of the device is increased. Moreover, the problem of current leakage between contiguous bit lines is resolved and the integration of the memory device is increased.
The present invention further provides a structure of a flash memory device and a fabrication method for the same, wherein the number of the manufacturing steps is reduced to increase the margin of the manufacturing process, and to reduce the cost and the time.
The present invention provides a structure of a flash memory device, wherein this flash memory device comprises a first conductive type substrate that already comprises a trench, a second conductive first well region located in the first conductive type substrate, a stacked gate structure disposed on the first conductive type substrate, a first spacer and a second spacer disposed on the sidewall of the stacked gate structure, wherein the top of the trench and the first spacer is connected. The flash memory device of the present invention further comprises a source region in the first conductive type substrate under the first spacer, a drain region in the first conductive type substrate under the second spacer, a first conductive type second-well region disposed between the stacked gate structure and the second conductive type first well region, wherein the junction between the first conductive type second well region and the second conductive first well region is higher than the bottom of the trench. Additionally, a doped region is disposed on the sidewall and the bottom of the trench, wherein this doped region electrically connects with the source region. A first contact that fills the trench in the first conductive type substrate, wherein the doped region isolates the first contact from the
Chen Chih-Ming
Hung Chih-Wei
Sung Da
Fahmy Jr. Wael
Jiang Chyun IP Office
Le Thao X.
Powerchip Semiconductor Corp.
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