Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-08
2001-09-18
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000
Reexamination Certificate
active
06291850
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 57883/1988, filed Dec. 23, 1998, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a capacitor in a dynamic random access memory (DRAM), and more particularly, to a structure of a lower electrode of a capacitor which inhibits occurrence of bridges between nodes, and to a method for fabricating the same.
2. Background of the Related Art
As a semiconductor memories have developed from millions of transistors on a single chip to billions of transistors on a single chip, a number of methods have been employed to increase an effective area of a capacitor within a restricted area of a cell in the semiconductor memory. For example, the effective area of the capacitor is increased by forming a three dimensional storage node, such as a trench type or a cylinder type. Further, a surface of a storage electrode used as a lower electrode of the capacitor is formed of HSG-Si (Hemispherical Grain-Silicon) that has a rough morphology rather than a smooth morphology, thereby increasing the effective area of the capacitor. Moreover, the three dimensional storage node approach and the HSG-Si approach can be combined.
The combined approach to increase the effective area of the capacitor will now be explained with reference to
FIGS. 1A-1D
.
FIGS. 1A-1D
illustrate cross-sections each showing a lower electrode of a capacitor (of a cylinder type) with an HSG-Si applied to it.
Referring to
FIG. 1A
, an interlayer insulating film
3
is deposited on a semiconductor substrate
1
having an impurity region
2
formed therein. Then, a portion of the interlayer insulating film
3
over the impurity region
2
is selectively removed, to form a contact hole for a capacitor storage electrode. Next, an amorphous silicon layer
4
is deposited. Preferably, the amorphous silicon layer
4
is formed of an amorphous silicon doped with phosphorus at a concentration of approximately 2.0×10
20
atoms/cm
3
.
As shown in
FIG. 1B
, an oxide film
5
is deposited on an entire surface of the device, and photoetched to selectively remove portions of the oxide film
5
, leaving the patterned oxide film
5
in a region around the contact hole. Then, the patterned oxide film
5
is used as a mask to selectively remove the amorphous silicon layer
4
. An amorphous silicon layer is deposited on an entire surface of the device and anisotropically etched to form amorphous silicon sidewalls
6
at sides of the patterned oxide film
5
. The amorphous silicon sidewalls
6
and the amorphous silicon layer
4
are electrically connected.
As shown in
FIG. 1C
, all of the oxide film
5
is removed, thereby forming lower electrode
7
of a cylindrical capacitor. As shown in
FIG. 1D
, silicon seeds are formed on a surface of the lower electrode
7
using a seeding gas (such as Si
2
H
6
or SiH
4
) at approximately 570-620° C. in an HSG-Si forming apparatus, and then annealed, to form an HSG-Si layer
8
with a rough surface. Thus, a cylindrical lower electrode
7
with an HSG-Si “mushroom” structure can be formed. Though not shown in these figures, by forming a dielectric film and an upper electrode in succession on the cylindrical lower electrode
7
, the capacitor is completed.
However, the capacitor and the method for fabricating the capacitor for a DRAM as described above has a number of problems. For example, with a gap below 0.2 &mgr;m between storage nodes of capacitors in the semiconductor memory with a high device packing density, and with the HSG-Si formed on a three dimensional structure like the cylindrical structure, the HSG-Si can fall off from regions with lower adhesive forces and subsequently remain between the storage nodes, without being removed even by a cleaning process. Thus, the HSG-Si can create bridges that cause electrical shorts between the nodes, mostly by the HSG-Si that has fallen off from peak points (end points in the cylindrical form) in the lower electrode. That is, the weak connection of a neck portion of the HSG-Si “mushroom” structure (resulting from a lack of the amorphous silicon required for formation of the HSG-Si due to a relatively thin amorphous silicon at the peak point) causes the fall-off or hang-down that formed bridges between adjacent nodes. Also, the HSG-Si connected to an external surface of the lower electrode can fall-off or hang-down in the course of cleaning or a high temperature annealing process, thereby causing bridges between adjacent nodes.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a structure of a lower electrode of a capacitor and a method for fabricating the same that substantially obviates one or more of the problems due to the limitations and disadvantages of the related art.
An object of the present invention is to provide a structure of a lower electrode of a capacitor and a method for fabricating the same which can inhibit occurrence of bridges.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in a first aspect of the present invention there is provided a structure of a lower electrode of a capacitor including a first lower electrode, second lower electrodes formed at both sides of the first lower electrode and electrically connected to and higher than the first lower electrode, and a Hemispherical Grain-Silicon (HSG-Si) layer formed on a top surface of the first lower electrode and inside walls of the second lower electrodes.
In another aspect of the present invention, there is provided a method for fabricating a capacitor comprising the steps of forming an interlayer insulating film on a semiconductor substrate, removing a portion of the interlayer insulating film to define a capacitor region, depositing a first thin semiconductor layer and a second thin semiconductor layer, depositing a planarizing insulating film on the second thin semiconductor layer, etching back the planarizing insulating film, and the first and second thin semiconductor layers until a surface of the interlayer insulating film is exposed, removing the planarizing insulating film and the interlayer insulating film to form a lower electrode, and forming a HSG-Si (Hemtispherical Grain-Silicon) layer on a surface of the second thin semiconductor layer.
In another aspect of the present invention, there is provided a method for fabricating a capacitor comprising the steps of forming an interlayer insulating film on a semiconductor substrate and having a contact hole, depositing a conductive layer and a planarizing insulating film on the interlayer insulating film and the contact hole, selectively removing the conductive layer and the planarizing insulating film to leave the conductive layer and the planarizing insulating film only in a capacitor-forming region, forming first semiconductor sidewalls at sides of the planarizing insulating film and connected to the conductive layer, forming second semiconductor sidewalls at sides of the first semiconductor sidewalls, removing the planarizing insulating film, and forming a HSG-Si (Hemispherical Grain-Silicon) layer on surfaces of the first semiconductor sidewalls.
In another aspect of the present invention, there is provided a lower electrode of a capacitor including a dielectric layer on a cylindrical lower electrode, and an upper electrode on the dielectric layer, the cylindrical lower electrode including a first bottom portion in contact with the plug, a second bottom portion on the first bottom portion and having different characteristics from the first bottom portion, a cylinde
An Jae Young
Choi Byung Jae
Kim Hong Seok
Rha Kwan Goo
Hyundai Electric Industries Co., Ltd.
Loke Steven
Morgan & Lewis & Bockius, LLP
Owens Douglas W.
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