Structure of contact between wiring layers in semiconductor inte

Details Structure of contact between wiring layers in semiconductor inte Structure of contact between wiring layers in semiconductor inte

1995-02-21

1997-04-01

Whitehead, Jr., Carl

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257758, 257775, 257776, H01L 2348, H01L 2352, H01L 2940, H01L 2328

Patent

active

056169612

ABSTRACT:
An insulation film is interposed between a first-level wiring layer and a second-level wiring layer. A contact hole is formed in the insulation film on the first-level wiring layer to electrically connect the first-level wiring layer and second-level wiring layer. The contact hole is larger than the width of the first-level wiring layer and second-level wiring layer. The second-level wiring layer is formed on a side wall and a bottom portion of the contact hole and electrically connected to the first-level wiring layer.

REFERENCES:
patent: 4916521 (1990-04-01), Kohyama
patent: 5200030 (1993-04-01), Cho et al.
patent: 5256564 (1993-10-01), Narita
Nesbit et al., A. 0.6um.sup.2 256 Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST), IEDM 93, 627-630 no date.
van Dijk et al., "A Two-Level Metallization System with Oversized Vias and a Ti:W Etch Barrier", IEEE VLSI Multilevel Interconnection Conference, Santa Clara Jun. 25-26, 1985, pp. 123-130.
Moriya, et al., "A Planar Metallization Process--Its Application to Tri-Level Aluminum Interconnection", IEDM 83, pp. 550-553 no date.

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