Structure of a trapezoid-triple-gate FET

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S288000, C257S327000, C257S329000, C257S330000, C257S331000, C257S332000, C257S333000, C257S334000

Reexamination Certificate

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06853031

ABSTRACT:
A structure of a Trapezoid-Triple-Gate Field Effect Transistor (FET) includes a plurality of trapezoid pillars being transversely formed on an crystalline substrate or Silicon-On-Insulator (SOI) wafer. The trapezoid pillars can juxtapose with both ends connected each other. Each trapezoid pillar has a source, a channel region, and a drain aligned in longitudinal direction and a gate latitudinally superposes the channel region of the trapezoid pillar. The triple gate field effect transistor comprises a dielectric layer formed between the channel region and the conductive gate structure.

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Intel Researchers; Three—Dimensional ‘Tri-Gate’ Transistors an Alernative to Traditional Flat Planar Transistors; Sep. 19, 2002;www.intel.com/pressroom.

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