Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-11-02
2003-02-18
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C438S011000, C438S014000, C438S015000, C438S018000
Reexamination Certificate
active
06521910
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a test key for monitoring self-aligned silicide (salicide) residue, and more specifically, to a structure of a test key for sensitively detecting induced leakage current caused by salicide residue on a spacer of a polysilicon line during a wafer acceptance test (WAT).
2. Description of the Prior Art
In front-end-of-line (FEOL) manufacturing for semiconductor devices, a self-aligned silicide (salicide) process is one of the most normally applied processes for reducing a resistance of word lines and gates as well as for reducing a sheet resistance of a source/drain. Generally the salicide process comprises steps of: (1) globally depositing a metal layer, such as a cobalt (Co) layer or a titanium (Ti) layer; (2) performing a thermal process, normally a rapid thermal process (RTP), to make the previously formed metal layer selectively react with a silicon substrate or a polysilicon gate so as to form a silicide layer; and (3) performing a post-cleaning process to remove portions of the unreacted metal layer. A prior art method of fabricating a salicide layer and that of the post-cleaning process are respectively disclosed in U.S. Pat. Nos. 6,221,766 and 5,316,977 and are omitted in the following discussion for simplicity of description.
However, the cleaning process does not ensure that the surface of the semiconductor wafer is completely cleaned and is without salicide residue after the cleaning process. An incomplete process frequently leads to salicide residue, causing induced leakage current, which seriously reduces the electrical performance of the semiconductor device, on a wall of a spacer on either side of the word line. As the production line width is reduced to 0.15 microns with reduced spacing in a subwavelength semiconductor process, the induced leakage current caused by salicide residue becomes a serious and intolerable disadvantage that frequently leads to scrapped batches of the product. To precisely assess the post-cleaning efficiency of a salicide process, a wafer acceptance test (WAT) is frequently employed after the post-cleaning process.
The WAT method includes providing several test keys distributed in a periphery region of a die to be tested. The test keys typically are formed on a scribe line between dies, and are electrically coupled to an external terminal through a metal pad. A module of the test keys is selected and each test key from the selected module is respectively used for a test of different properties of the wafer, such as threshold voltage (V
T
), saturation current (ID
SAT
), gate oxide thickness or leakage current. A controlled bias is applied to the test keys, and the induced current is read out to detect defects on the wafer. The structure of the test key employed for detecting leakage current of a salicide layer after the post-cleaning process is shown in FIG.
1
(
a
) and FIG.
1
(
b
).
Please refer to FIG.
1
(
a
) and FIG.
1
(
b
), which respectively represent portions of the layout of the test key for detecting salicide residue in a diffusion region, and that for detecting salicide residue on the spacer on either side of the polysilicon lines. At least two test keys are used for detecting induced leakage current caused by salicide residue after the salicide process according to the prior art. As shown in FIG.
1
(
a
), the test key for detecting salicide residue in the diffusion region comprises multiple first slim diffusion regions
12
arrayed along a first direction and multiple second slim diffusion regions
13
arrayed along a second direction, the first direction being anti-parallel to the second direction. Both the first slim diffusion regions
12
and second slim diffusion regions
13
are formed on a silicon substrate
10
, and the first slim diffusion regions
12
are alternately arrayed with the second slim diffusion regions
13
so that adjacent first slim diffusion region
12
and second slim diffusion region
13
, being isolated from each other by a shallow trench isolation (STI) region
14
, are anti-parallel to each other. The multiple first slim diffusion regions
12
are electrically connected to a circuit A, and the multiple second slim diffusion regions
13
are electrically connected to a circuit B. Normally, the circuit A is connected to a read out circuit and provided with a bias voltage of 1.5 volts, and the circuit B is grounded. As adjacent first slim diffusion region
12
and second slim diffusion region
13
are connected with each other due to an increasingly accumulated salicide residue
16
on adjacent first slim diffusion region
12
and second slim diffusion region
13
, a leakage current is detected.
As shown in FIG.
1
(
b
), the test key for detecting salicide residue on the spacer on either side of the polysilicon lines comprises multiple first slim polysilicon lines
22
arrayed along a first direction and multiple second slim polysilicon lines
23
arrayed along a second direction, the first direction being anti-parallel to the second direction. Both the first slim polysilicon lines
22
and second slim polysilicon lines
23
are formed on a silicon substrate
20
, and the first slim polysilicon lines
22
are alternately arrayed with the second slim polysilicon lines
23
so that adjacent first slim polysilicon line
22
and second slim polysilicon line
23
, being isolated from each other by an STI region
24
, are anti-parallel to each other. The multiple first slim polysilicon lines
22
are electrically connected to a circuit A, and the multiple second slim polysilicon lines
23
are electrically connected to a circuit B. Normally, the circuit A is connected to a read out circuit and provided with a bias voltage of 1.5 volts, and the circuit B is grounded. As adjacent first slim polysilicon line
22
and second slim polysilicon line
23
are connected with each other due to an increasingly accumulated salicide residue
26
on adjacent first slim polysilicon line
22
and second slim polysilicon line
23
, a leakage current is detected.
However, the test key for detecting salicide residue according to the prior art is not sensitive. As described in preceding paragraphs, leakage current is only detected as adjacent first slim diffusion region
12
and second slim diffusion region
13
, or adjacent first slim polysilicon line
22
and second slim polysilicon line
23
, are connected to each other due to the increasingly accumulated salicide residue
16
or
26
. Thus salicide residue merely on the first slim diffusion region
12
, or the first slim polysilicon lines
22
, is not detectable in this prior art method.
SUMMARY OF INVENTION
It is therefore a primary object of the present invention to provide a structure of a test key for sensitively detecting induced leakage current caused by self-aligned silicide (salicide) residue after a post-cleaning process of a salicide process.
It is another object of the present invention to provide a structure of a test key for detecting salicide residue on parallel slim diffusion regions or slim polysilicon lines.
According to the claimed invention, a structure of a test key for monitoring salicide residues comprises a silicon substrate, having at least a first diffusion region formed on the silicon substrate and at least a second diffusion region laterally formed on one side of the first diffusion region on the silicon substrate, a first polysilicon line and a second polysilicon line, each of the first and second polysilicon lines having two substantially vertical walls and a spacer formed on each of the two walls, formed on the silicon substrate across the first diffusion region and the second diffusion region, a dielectric layer covering the first polysilicon line, the second polysilicon line, the first diffusion region, and the second diffusion region, and a first metallic test finger and a second metallic test finger both orthogonal to the first polysilicon line and the second polysilicon line and both formed over the dielectric layer. A first contact
Hsu Winston
Loke Steven
United Microelectronics Corp.
Vu Quang
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