Structure of a stacked memory cell, in particular a...

Details Structure of a stacked memory cell, in particular a... Structure of a stacked memory cell, in particular a...

1999-08-02

2001-10-09

Meier, Stephen D. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S303000

Reexamination Certificate

active

06300654

ABSTRACT:

TECHNICAL FIELD
The present invention refers to a stacked type of memory cell structure. In particular, the memory cell described is of the ferroelectric non-volatile type, but the same structure can be used for DRAM cells.
BACKGROUND OF THE INVENTION
As is known and shown in
FIG. 1
, a ferroelectric cell
1
is composed of a MOS transistor
2
and a capacitor
3
having, as a dielectric, a ferroelectric material, for example PZT (PbZr
1−x
Ti
x
O
3
, perovskite) or SBT (SrBi
2
Ta
2
O
9
, layered perovskite). In detail, in the ferroelectric cell
1
, the NMOS-type transistor
2
has a source terminal
4
connected to a bit line BL, a gate electrode
5
connected to a word line WL and a drain terminal
6
connected to a first plate
7
of the capacitor
3
. A second plate
8
of the capacitor
3
is connected to a plate line PL.
The cell is capable of storing binary information thanks to the hysteresis characteristics of the ferroelectric material which is sandwiched between the plates
7
and
8
and which, when there are no applied voltages, can assume two bias states depending on the sign of previously-applied voltage across the capacitor
3
terminals.
All currently-known ferroelectric cells can be classified into two families: strapped cells and stacked cells.
In strapped cells, an embodiment of which is shown in
FIG. 2
, the capacitor
3
is constructed above a field oxide region
10
that delimits an active area
11
of the substrate
12
in which the conductive regions (source
13
and drain
14
) of the transistor
2
are formed. In detail, the first plate
7
of the capacitor
3
is here placed on top and is made of a square- or rectangular-shaped region of conductive material (for example, platinum), connected to the drain region
14
of the transistor
2
through a metallic connection line
16
; the second plate
8
of the capacitor
3
is here placed underneath and is made by a band of conductive material (for example, platinum again) which runs perpendicular to the drawing plane and forms a plate line PL, connected to other capacitors of adjacent cells; a dielectric region
17
, of ferroelectric material, is sandwiched between the first plate
7
and the second plate
8
. The gate electrode
5
of the transistor
2
is made of a band of polycrystalline silicon which runs perpendicular to the drawing plane and forms a word line WL.
In stacked cells, an embodiment of which can be seen in
FIG. 3
, the capacitor
3
is constructed above the active area
11
, directly above the drain region
14
of the transistor
2
. In this case, the first plate
7
of the capacitor
3
is placed underneath and is made by a square- or rectangular-shaped region of conductive material (for example, platinum) connected to the drain region
14
through a contact
23
formed in an opening of a protective layer
24
(for example BPSG) and the second plate
8
, of conductive material, is placed above and is connected to a metalization band
25
defining the plate line PL.
A titanium/titanium nitride region
26
runs below the first plate
7
to help the adhesion of the first plate
7
of the capacitor
3
on the protective layer
24
.
The architecture of a array
28
of ferroelectric stacked or strapped cells
1
is shown in FIG.
4
. It will be noted that the ferroelectric cells
1
are placed on rows and columns and are coupled so that the cell pairs
27
are placed parallel to bit lines BL; the transistors
2
of each cell pair
27
have common source regions, connected to the same bit line BL; and the capacitors
3
belonging to the cell pairs
27
adjacent in a parallel direction to the bit lines BL are connected to adjacent plate line pairs PL.
Ferroelectric stacked cells
1
are currently preferred, since they are the only ones capable of meeting the scalability requirements of new CMOS technologies. In stacked cells, the layout rules on the capacitor
3
design are crucial for the optimization of the cell.
SUMMARY OF THE INVENTION
There are therefore several known embodiments for stacked cells, apart from that shown in
FIG. 3
, in which both plates
7
,
8
and dielectric region
17
are defined using a single mask and forming the plate line PL via a special metallic band. For example, according to another known arrangement, the first (lower) electrode
7
is formed by a separately-shaped conductive region, while the dielectric region
17
and the second (upper) electrode
8
are mutually aligned and shaped using a single mask.
In all these cases, the connection of at least one of the plates
7
,
8
with the same mask used for the connection of the ferroelectric material composing the dielectric region
17
is critical; for example, during connection, slightly volatile components are formed, and these can be redeposited along the capacitor edge and damage its active zone, causing a decay in the ferroelectric properties of the capacitor, with an increase in edge losses and lower voltage strength.
On the other hand, the separate definition of the three parts constituting the capacitor
3
(first and second plates
7
,
8
and dielectric region
17
), which would allow the problem presented by current manufacturing processes to be solved, causes an increase in overall dimensions that is in conflict with present trends towards miniaturization. In fact, in making definition masks, account must be taken of both manufacturing tolerances (at present, with a 0.35 &mgr;m process, equal to 0.2 &mgr;m) and the minimum distances between the lower adjacent plates and the upper adjacent plates (for example, equal to 0.4 &mgr;m). In particular, with the conditions given above, it would be necessary for the lower plate
7
to be wider, with respect to the dielectric region
7
, by an amount at least equal to the manufacturing tolerance (at least 0.2 &mgr;m) on each side; similarly, it would be necessary for the dielectric region
17
to be wider, with respect to the upper plate
8
, by the same amount; therefore, taking into account the minimum distance between the lower plates
7
, the resulting overall dimensions for the capacitors
3
and consequently for the ferroelectric cells
1
are excessive.
An object the present invention is making a stacked memory cell, without the described disadvantages. According to the present invention, a stacked memory cell is realized as claimed in Claim
1
.
In practice, according to the invention, the dielectric regions of at least two adjacent cells in the direction of the bit lines are no longer separate. In particular, the dielectric region
17
can be continuous and shared between the two adjacent capacitors belonging to pairs of adjacent cells. In this way, the layout definition rules for capacitor scalability are given only by the distance between two lower adjacent electrodes and by the lateral space (enclosure) between upper electrode and lower electrode. This allows, with the same cell area, maximizing the working area of the capacitor compared with the layout of the arrangement where three different masks for definition of the capacitor are used and the dielectric region is divided between adjacent cells in the direction of the bit lines. This causes an increase in signal amplitude (proportional to the active area of the capacitor) supplied by each cell to the sense amplifier during reading. Alternatively, it is possible to obtain a reduction in the area occupied by the ferroelectric cells.


REFERENCES:
patent: 5519237 (1996-05-01), Itoh et al.
patent: 5796133 (1998-08-01), Kwon et al.
patent: 5955758 (1999-09-01), Sandhu et al.
patent: 6028361 (2000-02-01), Ooishi
patent: 6063656 (2000-05-01), Clampitt
Amanuma, K. et al., “Capacitor-on-Metal/Via-stacked-Plug (CMVP) Memory Cell for 0.25um CMOS Embedded Fe RAM”,IEEE, 1998, pg. 363-366.
Yamazaki, T., et al., “Advanced 0.5um FRAM Device Technology with Full Compatibility of Half-Micron CMOS Logic device”,Advanced Process Integration Department, Fujitsu Limited.(4 pages), (date unknown).
Takashima, D. et al., “A Sub-40ns Random-Access Chain FRAM Architecture with a 7ns Cell-Plate-Line Drive,”IEEE I

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