Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
1999-11-09
2001-11-13
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S724000
Reexamination Certificate
active
06316828
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to the structure of a solder mask for the circuit module of BGA substrate and more particularly to the openings in the structure of the solder mask for the electronic devices between the power ring and ground ring or between two through-holes.
2. Description of the Related Art
An integrated circuit needs power to operate and it has a plurality of wires connecting the power to the I/O ports of the integrated circuit. The wires themselves are the source of electromagnetic interference, especially when the integrated circuit transmits at high frequency. The wires of the integrated circuit emit electromagnetic interference which influences the normal operation of the integrated circuit. A capacitor is electrically connected to the wires and can reduce the electromagnetic interference of the wires.
U.S. Pat. No. 5,906,700, issued on May 25, 1999 to Furukawa et al., discloses a method of manufacturing a circuit module, as shown in
FIG. 1. A
substrate
100
has a chip
101
and a plurality of electronic parts
102
, and an encapsulant
103
encapsulates the chip
101
and a portion of the electronic parts
102
. However, the dimensions of the surface of the substrate
100
are limited around the periphery of the chip
101
, and the electronic parts
102
must therefore be placed in an area farther away from the chip
101
on the substrate
100
due to the arrangement of the traces electrically connecting to the wires. Therefore, U.S. Pat. No. 5,906,700 fails to meet the requirement that the electronic parts
102
be arranged close to the chip
101
and necessitates rearrangement or addition of more traces, which complicates the process.
U.S. Pat. No. 5,825,628, issued on Oct. 20, 1998 to Garbelli et al., discloses an electronic package, as shown in
FIG. 2. A
substrate
200
is a multi-layer PCB and includes a power layer
201
connecting to a hole
202
and a ground layer
203
connecting to a hole
204
. A chip
210
is adhesively attached to the substrate
200
and is enclosed by an encapsulant
211
. An electronic part connects the hole
202
to the hole
204
for reduction of electromagnetic interference. The electronic part has a defined longitudinal distance but U.S. Pat. No. 5,825,628 must leave an area on its surface for the arrangement of a hole
202
to connect to the power layer
201
and the hole
204
to the ground layer
203
. Because U.S. Pat. No. 5,825,628 must save a particular area for this electronic part, and further necessitates the manufacture of a new hole
202
to connect to the power layer
201
and a new hole
204
to connect to the ground layer
203
in this area. Thus the substrate
200
of U.S. Pat. No. 5,825,628 increases the complexity of the hole and the manufacture of traces. It also increases the limitation of the dimensions of substrate so that U.S. Pat. No. 5,825,628 fails to meet the requirement that the electronic part be close to the chip. The method of providing holes in substrate
200
is adapted to a multi-layer PCB, and the method of proving a hole to connect to the power layer or the ground layer cannot be applied to the dual-layer PCB without leaving space for the arrangement of the power layer or the ground layer.
The present invention intends to provide the structure of a solder mask for the circuit module of a BGA substrate with openings provided on the power ring, the ground ring and the original holes in such a way as to mitigate and overcome the above problem. Therefore, the openings are provided for the arrangement of the electronic part on the original holes and traces to reduce the density of the traces of the substrate.
SUMMARY OF THE INVENTION
The primary objective of this invention is to provide the structure of a solder mask for the circuit module of a BGA substrate in such a way that has the openings on the power ring, the ground ring and the original holes do not necessitate leaving space for the arrangement of the holes and the traces for electronic parts and thus brings the electronic part closer to the chip and simplifies the structure of the substrate.
The present invention is the structure of a solder mask for the circuit module of a BGA substrate. The substrate mainly comprises a power ring, a ground ring, a plurality of holes, a plurality of first holes and a plurality of second holes. The power ring and the ground ring are arranged between the chip area and the wire bonding area. The first openings are arranged on the power ring and the ground ring for receiving the electronic part. Thus the substrate meets the requirement of keeping the electronic part close to the chip. The second openings are arranged over the associated holes to electrically connect to the power ring and the ground ring via traces. These holes do not need to electrically connect the power layer and the ground layer of the substrate. The openings of the present invention use the power ring, ground ring and the holes of the substrate to electrically connect to the electronic parts, so the present invention does not necessitate the provision of other holes or traces and simplifies the structure of the substrate. The distance between the two openings of the present invention can, moreover, be adjusted according to the length of the electronic part.
Other objectives, advantages and novel features of the invention will become more apparent from the following detailed description and the accompanying drawings.
REFERENCES:
patent: 5640048 (1997-06-01), Harada
patent: 5825628 (1998-10-01), Garbelli et al.
patent: 5906700 (1999-05-01), Furukawa
patent: 6091144 (2000-07-01), Harada
Chen Tao-Yu
Hsu Kao-Yu
Tao Su
Advanced Semiconductor Engineering Inc.
Bacon & Thomas
Potter Roy
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