Structure of a field effect transistor having metallic...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S377000, C257S768000, C257S757000, C257SE21199, C257SE21439, C257SE21438, C257SE21440, C438S233000, C438S655000, C438S656000

Reexamination Certificate

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09825973

ABSTRACT:
A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of a source and a drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometaric metallic silicides is X0to Y0. X, Y, X0and Y0satisfy the following inequity: (X/Y)>(X0/Y0).

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patent: 6344675 (2002-02-01), Imai
Deep sub-0.1 um MOSFET's with Very Thin SOL Layer for Ultra-Low Power Applicants, Information and Communication Engineers C-II vol. J81-C-II No. 3, pp. 313-319, Aug. 1998.
Optimization of Series Resistance in Sub-0.2 um SOI MOSFET's, IEEE Electron Device letters, vol. 15, No. 9, Sep. 1994, p. 363-365.
Optimization of series resistance in Sub-0.2 um SOI MOSFET's, 1993 IEEE, pp. IEDM93-723-726-IEDM 93.

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