Structure of a deep trench-type DRAM

Details Structure of a deep trench-type DRAM Structure of a deep trench-type DRAM

2002-01-14

2004-08-31

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S297000, C257S304000

Reexamination Certificate

active

06784477

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a structure and a method for fabricating semiconductor memory devices including random dynamic access memory (DRAM) devices. More particularly, the present invention relates to a structure and method of fabricating a DRAM device with deep trench capacitors.
BACKGROUND OF THE INVENTION
As semiconductor integration continuously increases, device dimensions are necessarily accordingly decreased. Hence the conventional scaling techniques are limited by the stringent leakage requirement of devices. A conventional DRAM cell has a 2-dimensional transistor even though the capacitor thereof has a 3-dimensional design. The integration of DRAM cell array is thereby limited.
Grurning et al. suggest that a sub-8F2 DRAM cell comprising a deep trench capacitor and a vertical transistor both in a deep trench can greatly increase the integration of DRAM cells (A Novel Trench DRAM Cell with a Vertical Access Transistor and Buried Strap (VERI BEST) for 4 Gb/16 Gb, p25, 1999 IEDM). Generally speaking, the traditional DRAM with a deep trench structure comprises a buried strap. The contact resistance of the buried strap (BSRc) is a critical parameter of a DRAM device and is hard to control well.
Specifically, reference is made to
FIG. 1
, which illustrates a top view of the surface of the substrate
10
of a DRAM memory device. In the figure are shown a capacitor array
12
, a plurality of AA (active area) islands for controlling the capacitors in capacitor array
12
and shallow trench isolation regions
14
electrically insulating between the AA islands. In addition, it is noted that the row direction of the capacitor array illustrated in
FIG. 1
is the direction of a bit line and the column direction of the capacitor array is the direction of a word line.
Reference is made to
FIG. 2
, which is the cross-sectional view taken along line
1
—
1
of FIG.
1
. Each capacitor has a deep trench structure
16
, which can be divided into an upper portion and a lower portion. The lower portion further comprises a bottom plate
18
, a capacitor dielectric layer
20
and one part of a top plate
22
. The upper portion comprises the other part of the top plate
22
, a collar oxide layer
24
and a buried strap layer
26
. For the purpose of electrical insulation between two capacitors, the active area of a DRAM device with deep trench structures traditionally has an island pattern.
However, as semiconductor integration continuously increases, dimensions of capacitors are accordingly decreased. The process window of photolithography is limited by the narrow distance between neighboring capacitors when patterning AA islands, described above. Moreover, the originally designated pattern of an active area is a rectangular. Under the influence of the optical effect, the real pattern of the active area is an island with the corners rounded. Accordingly, so far, sub-wavelength photolithography is used in the sub-quarter micron technology. Various resolution enhanced technologies (RET), such as optical proximity effect correction (OPC) and phase shift mask, must be applied in critical photo steps, but these further complicate the layout design and mask making.
Both a narrow process window of photolithography and complex resolution enhanced technology always make patterns lose their fidelity to their original design, which seriously affects device parameters. More specifically, the overall contact resistance of the buried strap is directly correlated to the intersection of the periphery of a deep trench and an AA pattern. A worst case scenario of alignment error between a deep trench structure and an active area along a bit line direction is shown in FIG.
3
.
Compared with
FIG. 2
, which shows an ideal case of a DRAM device without any defects as described above,
FIG. 3
shows a practical case with some defects, for example, a misalignment between a deep trench structure and an active area. More specifically, owing to alignment error, the top plate
22
does not contact the buried strap
26
well in the left capacitor of a capacitor subassembly, and accordingly, the left capacitor loses its intended function and fails.
SUMMARY OF THE INVENTION
It is an objective of this invention to provide a design of a DRAM device with deep trench structures to increase semiconductor integration.
It is another objective of this invention to provide strip-type active areas of a DRAM device to improve a process window of active area patterning and also reduce the contact resistance of a buried strap.
According to the objectives described above, the present invention discloses a DRAM device. The DRAM device comprises a plurality of strip-type active areas on a substrate, a plurality of shallow trench isolation regions on the substrate for isolating each of the active areas, a plurality of word lines above the active areas and the shallow trench isolation regions, and an array formed by overlapping the word lines and the active areas. The array includes a plurality of first overlapping portions and a plurality of second overlapping portions, with every two of the first overlapping portions separated by every two of the second overlapping portions on each of the active areas. Each of the first overlapping portions is next to each of the second overlapping portions on every two the neighboring active areas and a capacitor array on the active areas. Each of the capacitors is on each of the first overlapping portions, with the capacitor including a deep trench structure and a collar isolation. A memory cell is formed by the word line on one of the second overlapping portions and the capacitor on one of the first overlapping portions.
The present invention also discloses a method of fabricating a DRAM device. The DRAM comprises a substrate having a pad oxide layer and a silicon nitride layer formed in turn thereon and an capacitor array. Each of the capacitors has a deep trench structure therein. Every two of the capacitors are a capacitor subassembly. The capacitor subassemblies on a row of the capacitor array are not next to each other, while the capacitor subassemblies in the neighboring rows of the capacitor array are not next to each other. The method is to form a collar oxide layer on an upper sidewall region of the deep trench structure and then form a bottom plate on an interface region of the substrate and a lower sidewall portion of the deep trench structure. A dielectric layer is formed on an internal surface of the bottom plate in the deep trench structure by utilizing the collar oxide as a mask. A top plate is formed in the deep trench structure to cover the dielectric layer. Part of the collar oxide layer is removed to form a first collar portion and a second collar portion, in which the first collar portion is the adjacent portion of the collar oxide layer in the two capacitors of the capacitor subassembly and the second collar portion is the non-adjacent portion of the collar oxide layer in the two capacitors of the capacitor subassembly. The first collar portion is longer than the second collar portion in the depth direction of the deep trench structure. The first collar portion is used to isolate the neighboring capacitors and the second collar portion is used to reduce sufficiently a leakage current of the substrate surrounding thereof. A buried strap conductive layer is formed above the second collar portion and the top plate. A plurality of strip-type active areas and a plurality of shallow trench isolation regions are formed in turn thereon. A gate oxide layer is formed thereon and a plurality of word lines is formed on the columns of the capacitor array. An array is formed by overlapping the word lines and the active areas; the array includes a plurality of first overlapping portions and a plurality of second overlapping portions, with each of the first overlapping portions therein comprising each of the capacitor subassemblies. Finally, a plurality of sources and drains is formed on two sides of each the second overlapping portions, with a memory cell bein

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