Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-03-10
2001-03-06
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S702000, C438S666000, C438S692000, C438S633000
Reexamination Certificate
active
06197682
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same, more particularly to a structure of a contact hole which contacts with upper and lower wiring layers in a multilayer wiring structure of the semiconductor device and to a manufacturing method of the same.
2. Description of the Prior Art
How to constitute a multilayer wiring has been a critical technology at a realization of micronization of semiconductor devices. As micronization of the semiconductor devices is advanced, widths of wiring layers of layers constituting the multilayer wiring, intervals between wirings and diameters of contact holes to connect upper and lower wiring layers have been reduced, respectively.
The importance in this multilayer wiring technology is what kinds of multilayer wiring structures should be adopted, to avoid the connection of the upper wiring layer and an intermediate wiring layer and to connect directly the upper and lower wiring layers, and moreover how to manufacture such multilayer wiring structure.
Recently, such multilayer wiring structure has a tendency to adopt the structure in which a contact hole (a self-aligned contact hole) penetrating through the intermediate wiring layers is formed in these layers in a self-aligned manner and the upper and lower wiring layers are connected directly thorough this contact hole.
As an example of such technology, there has been a manufacturing method of the self-aligned contact hole disclosed in U.S. Pat. No. 531,892, published on Jun. 7, 1994. The specification of this United States Patent discloses a forming method of a node contact hole of a DRAM having a COB (Capacitor-Over-Bit-Line) structure in which a storage node electrode of a stacked type is formed on a bit line.
Referring to
FIGS. 30 and 31
showing schematically sectional views of manufacturing steps of the self-aligned contact hole, the manufacturing method of the self-aligned contact hole, recited in the specification of the foregoing United States patent is as follows.
First of all, a field oxide film
402
is formed on an element isolation region formed in the surface of a semiconductor substrate
401
, and a gate oxide film (not shown) is formed on an element formation region. After word lines are formed, source diffusion layers
408
a
and
408
b
and drain diffusion layers (not shown) are formed in the element formation region in the surface of the semiconductor substrate
401
. A first interlayer insulating film
412
is formed on the entire surface of the resultant structure. Bit contact holes (not shown) reaching the drain diffusion layer are formed in the interlayer insulating film
412
. Bit lines
418
a
,
418
b
and
418
c
are formed on the interlayer insulating film
412
. These bit lines
418
a
,
418
b
and
418
c
are connected to the drain regions corresponding bit contact holes. Since the bit lines
418
a
,
418
b
and
418
c
are formed for the corresponding source diffusion layers
408
a
and
408
b
in a self-aligned manner, for example, the bit line
418
a
comes to overlap with the source diffusion layer
408
a.
Subsequently, second interlayer insulating film
422
covering the bit lines
418
a
,
418
b
and
418
c
is formed on the entire surface of the resultant structure. A photoresist film
471
having openings located just above the source diffusion layers
408
a
and
408
b
is formed on the surface of the interlayer insulating film
422
. Using the photoresist film
471
as a mask, the interlayer insulating film
422
is subjected to a selective anisotropic etching. The anisotropic etching at this time is ceased before the upper surface of the interlayer insulating film
412
is exposed, and, moreover, a thickness of the interlayer insulating film
422
which remains after the anisotropic etching is regulated such that it becomes thinner than that of the bit lines
418
a
and
418
b
. Thus, at least each one part of the overlapping portions in the bit lines
418
a
and
418
b
with the source diffusion layer
408
a
is exposed (
FIG. 30
a
).
Next, using the photoresist film
471
as a mask, the bit lines
418
a
and
418
b
are subjected to a selective anisotropic etching. As a result, the portions of the bit lines
418
a
and
418
b
exposed at the selective anisotropic etching for the interlayer insulating film
422
are removed (
FIG. 30
b
) Subsequently, using the photoresist film
471
as a mask, the interlayer insulating films
412
and
422
are subjected to a selective anisotropic etching. Hence, node contact holes
434
reaching the source diffusion layers
408
a
and
408
b
are formed (
FIG. 30
c
).
After the photoresist film
471
is removed, an insulating film (not shown) having a predetermined thickness is formed on the entire surface of the resultant structure. This insulating film is etched-back so that insulating film spacers
436
are formed on the side surfaces of the node contact holes
434
. Provisions of these insulating film spacers
436
result in the self-alignment of the node contact holes
434
with the bit lines
418
a
and
418
b
(
FIG. 31
a
).
Next, storage node electrodes
438
a
and
438
b
connected to the corresponding source diffusion layers
408
a
and
408
b
through the node contact holes
434
are formed (
FIG. 31
b
).
The manufacturing method of the self-alignment contact hole, recited in the foregoing U.S. Pat. No. 5,318,925, in which in the DRAM having memory cells of the COB structure the node contact holes can be formed without broadening the widths of the bit lines, is extremely effective for the DRAM which gives the highest priority to the micronization of cell size of the memory cell. In the case of the DRAM, even if the width of the bit line is locally narrower and the effective diameter of the node contact hole is reduced, severe obstacles are not brought about.
It is not desirable that the manufacturing method of the self-aligned contact hole, disclosed in the foregoing U.S. Pat. No. 5,318,925, is applied to the semiconductor device giving the highest priority to a high speed operation, which is typified by logic circuits. In such semiconductor device, an increase in a resistance, such as an increase in a contact resistance due to a reduction in the effective diameter of the contact hole, is a severe obstacle to the high speed operation of the semiconductor device. Furthermore, in such semiconductor device, a high current density, at least in a moment, in the wiring layer is high so that the local increase in the resistance of the wiring layer leads to deterioration of a migration resisting property in the portion where the resistance is locally increased. These problems are solved by broadening the interval between the wirings serving as the intermediate layers. In this case, the self-alignment contact hole is unnecessary. Hence, such technique runs to the requirement of the micronization in the semiconductor devices.
SUMMARY OF THE INVENTION
In a semiconductor device having a multilayer wiring structure which includes contact holes connecting directly upper and lower wiring layers without a connection of the upper wiring layer to a wiring layer of an intermediate layer, the object of the present invention is to provide a semiconductor device giving a highest priority to a high speed operation, which has a structure capable of suppressing an increase in a contact resistance without injuring a migration resisting property and without a sacrifice of micronization of the device, and to provide a manufacturing method of the same.
A semiconductor device of the present invention comprises a first insulating layer covering a semiconductor substrate; a first wiring selectively formed on the first insulating layer; a second insulating layer covering surfaces of the first insulating layer and the first wiring; a first opening selectively formed in the second insulating layer, the first opening penetrating through a portion of the first wiring to divide the first wiring to first and second portions; a conductive lay
Drynan John Mark
Koyama Kuniaki
Everhart Caridad
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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