Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Patent
1997-04-25
1999-07-06
Chaudhuri, Olik
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
257640, 257649, 257760, 257763, H01L 2358
Patent
active
059200812
ABSTRACT:
A structure of a bond pad to prevent probe pin contamination is disclosed herein a first conductor layer is formed on the substrate. A passivation layer including a titanium nitride layer, a silicon nitride layer, and a silicon oxide layer is formed on the first conductor layer. A photoresist layer is patterned on the passivation layer to define a contact hole, and then etching the passivation layer using the photoresist layer as a mask to form the contact hole. A second conductor layer serving as a top metal of bond pad harder than the first conductor layer is selectively deposited on the first conductor layer, and filled in the contact hole. The present invention can reduce a probe pin contamination so that extend the probe pin lifetime using this selective deposition technique to form the pond pad structure. Additionally, the structure can prevent the contact resistance between the probe pin head and the bond pad increasing, and reduce the probe pin overkill ratio.
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Chen Shyn-Ren
Wu Chii-Ming Morris
Chambliss Alonzo
Chaudhuri Olik
Taiwan Semiconductor Manufacturing Co. Ltd.
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