Structure nonvolatile semiconductor memory cell array and method

Details Structure nonvolatile semiconductor memory cell array and method Structure nonvolatile semiconductor memory cell array and method

1998-08-12

2000-10-10

Elms, Richard

Static information storage and retrieval

Floating gate

Particular connection

36518505, 365 63, 365 51, G11C 1604

Patent

active

061308382

ABSTRACT:
A nonvolatile semiconductor memory cell array is shown which is composed of a plurality of unit cell-arrays arranged in a repeating pattern. Each of the unit cell-arrays includes a first plurality of cell transistors having control gates coupled in common to a first word line and a second plurality of cell transistors having control gates coupled in common to a second word line. The two word lines are arranged in parallel to one another and perpendicular to a bit line. The bit line is connected in common with drains of both the first and second plurality of cell transistors through a bit line contact. A pair of source lines is arranged along each side of the bit line and parallel to the bit line. Each source line is coupled to one transistor from each of the first and second pluralities of cell transistors through a source line contact.

REFERENCES:
patent: 4962481 (1990-10-01), Choi et al.
patent: 5434814 (1995-07-01), Cho et al.
patent: 5464999 (1995-11-01), Bergemont
Satyen Mukherjee et al., "A Single Transistor EEPROM Cell and Its Implementation in a 512K CMOS EEPROM," "EDM, pp. 616-619, 1995.

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