Structure, material, and design for assembling a low-K Si...

Details Structure, material, and design for assembling a low-K Si... Structure, material, and design for assembling a low-K Si...

2008-09-23

2008-09-23

Weiss, Howard (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Encapsulated

With specified encapsulant

C257S643000, C257S787000, C257S656000, C257S727000, C257S734000

Reexamination Certificate

active

10719218

ABSTRACT:
Provided are semiconductor low-K Si die wire bonding packages with package stress control and fabrication methods for such packages. The packages include molding interface material applied onto the low-K Si die. In general, the molding interface material is selectively applied onto the low-K Si die surface in order to minimize to safe levels the package stress experienced by the low-K Si die. Selective application includes defining various combinatorial patterns of coated and non-coated regions. In addition, selective application may also include a general application of molding interface material to create a stress buffer zone. The results are packages with less stress experienced by the low-K Si die and so improved reliability (in compliance with industry specifications).

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