Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2006-05-09
2006-05-09
Pham, Hoai (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S734000, C257S758000
Reexamination Certificate
active
07042097
ABSTRACT:
A structure for reducing stress-induced voiding in an interconnect of an integrated circuit, the interconnect having a first portion and at least a second portion narrower than the first portion. The structure comprises at least one interior slot disposed in the first portion in proximity to the intersection of the first portion and the second portion. The present invention also includes methods of making the interconnect and the structure. A conductive interconnect structure comprises a first portion and at least a second portion narrower than the first portion; and a stress reducing structure comprising a transition portion formed at an intersection of the first portion and the second portion.
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Timothy D. Sullivan, “Stress-Induced Voiding In Microelectronic Metallization: Void Growth Models and Refinements”, Annual Review Of Materials Science, (1996), vol. 26: pp. 333-364.
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Hsia Chin-Chiu
Wan Wen-Kai
Yao Chih-Hsiang
Duane Morris LLP
Nguyen Dilinh
Pham Hoai
Taiwan Semiconductor Manufacturing Co. Ltd.
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