Structure for reducing parasitic leakage in a memory array with

Details Structure for reducing parasitic leakage in a memory array with Structure for reducing parasitic leakage in a memory array with

1994-08-03

1995-09-05

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257301, 257394, 257519, H01L 2976

Patent

active

054480906

ABSTRACT:
A semiconductor structure of merged isolation and node trench construction is presented, along with a method of fabrication, wherein an isolation implant layer is formed at the intersection of the storage node, isolation trench and field isolation region. The isolation implant layer has higher concentration of implant species than the adjacent field isolation region and is positioned to prevent a parasitic leakage mechanism between the source/drain diffusion of the storage node and an adjacent bit line contact diffusion. Implantation occurs during memory structure fabrication through the deep trench sidewall near the upper surface of the substrate.

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Soychak, F. J. et al., "Technique to Selectively Dope Semiconductor Trench Walls and Bottom," IBM Technical Disclosure Bulletin, vol. 30, No. 8, pp. 268-269, Jan. 1988.

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