Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1996-08-15
1998-11-03
Saadat, Mahshid D.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257369, 257372, 257374, 438228, 438526, 438529, H01L 2976, H01L 2994
Patent
active
058313133
ABSTRACT:
A structure for improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, a substrate has an upper surface and a first dopant region formed therein. The first dopant region has a lower boundary located below an upper surface of the substrate and a side boundary extending from the upper surface of the substrate to the lower boundary of the first dopant region. A heavily doped region having a first portion and a second portion located along the lower boundary and the side boundary of the first dopant region, respectively, has a substantially uniform dopant concentration greater than a dopant concentration of the first dopant region. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.
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Photocopy of materials presented at a seminar hosted by Genus, Inc. on Jul. 12, 1995 in San Francisco, California entitled, "Manufacturing Issues (Process & Equipment) in MeV Implantation", John O. Borland.
Hayden, James D. et al., "A High-Performance Half-Micrometer Generation CMOS Technology for Fast SRAM's", IEEE Transactions on Electron Devices 38:876-884 (1991).
Lewis, Alan G. et al., "Latchup Performance of Retrograde and Conventional n-Well CMOS Technologies", IEEE Transactions on Electron Devices 34:2156-2163 (1987).
Choi Jeong Yeol
Han Chung-Chyung
Lien Cheun-Der
Integrated Device Technology Inc.
MacPherson Alan H.
Martin Wallace Valencia
Saadat Mahshid D.
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