Structure for hub for supporting high capacity memory subsystem

Details Structure for hub for supporting high capacity memory subsystem Structure for hub for supporting high capacity memory subsystem

2011-08-09

2011-08-09

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S005000, C711SE12001

Reexamination Certificate

active

07996641

ABSTRACT:
A design structure is provided for a hub for use in a high-capacity memory subsystem in which memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.

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