Structure for ESD protection in semiconductor chips

Details Structure for ESD protection in semiconductor chips Structure for ESD protection in semiconductor chips

1997-06-05

1998-06-16

Meier, Stephen

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257382, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

057675520

ABSTRACT:
An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor. The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas, have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.

REFERENCES:
patent: 4691217 (1987-09-01), Ueno et al.
patent: 4822749 (1989-04-01), Flanner
patent: 5051860 (1991-09-01), Lee et al.
patent: 5066999 (1991-11-01), Casper
patent: 5304502 (1994-04-01), Hanagasaki
patent: 5440163 (1995-08-01), Ohhashi
patent: 5565698 (1996-10-01), Obermeier

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