Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-11-16
2004-03-09
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S202000, C257S206000, C257S208000, C257S347000, C257S348000, C257S349000, C257S350000, C257S351000, C257S352000, C257S353000, C257S354000, C257S374000, C257S401000, C257S903000
Reexamination Certificate
active
06703641
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor processing and testing, and more particularly to an in-line monitor structure sensitive to charging effects associated with various device processing methods including plasma processes.
BACKGROUND OF THE INVENTION
In the manufacture of devices on a semiconductor wafer, a number of processes presently in use involve plasmas or particle beams incident on the wafer surface. Examples of such processes include plasma sputtering, reactive ion etching, plasma etching, ionized phase vapor deposition, e-beam processing and ion implantation. It is known that devices built with SOI (silicon-on-insulator) technology are susceptible to damage resulting from the manufacturing processes (see T. Poiroux et al., “Plasma process induced damage in SOI devices,” IEDM November 1999). In particular, these processes may cause localized buildup of electrical charge in the silicon device layer. This charge buildup (also called floating-body effect) can compromise device performance, as well as introduce changes in device characteristics that are difficult to detect. This problem is especially acute in processes employing a hollow cathode magnetron, ionized phase vapor deposition, or other apparatus in which the wafer is subjected to a DC bias.
Electrical testing of devices while the devices are still on the manufacturing line (“in-line monitoring”) is typically done using monitor structures located in the kerf areas between chips. For example, as shown in
FIG. 1A
, the kerf area
2
between chips
1
is populated with monitor structures
3
. An effective monitor structure must be sensitive to any effects which may result in failure of the chips. There is a need for a monitor structure which is capable of detecting subtle, localized charging effects due to plasma processing in SOI technologies.
SUMMARY OF THE INVENTION
The present invention addresses the above-described need by providing a semiconductor device monitor structure which can detect localized defects due to floating-body effects, particularly on SOI device wafers.
The monitor structure of the present invention comprises a plurality of cells containing FET devices; the cells are disposed at a perimeter of the structure. Each of the cells includes polysilicon gate structures having a characteristic spacing given by a first distance, and a portion extending beyond the perimeter a second distance. The first distance and said second distance are non-uniform between cells in the structure (as in the case of cells constructed in accordance with progressively varying ground rules). This monitor structure may be bordered by an insulating region such as a shallow trench isolation (STI) region, with the portion extending beyond the perimeter extending into the STI region. The FET devices may be either PFET or NFET devices. The cells may advantageously be bit fail mapped for single-cell failures, thereby enabling detection of localized defects due to floating-body effects. In addition, the cells may be viewed as comprising an SRAM cache, so that an SRAM cache failure indicates a defect due to floating-body effects.
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Monitoring Floating-Body Charge in PD/SOI CMOS Devices, J.B. Kuang, M.J. Saccamango, and S. Ratanaphanyarat, IBM Corporation, Advanced Server Development—Symp. VLSI Circuits, Jun. 2001.
Cambra, Jr. Malcolm P.
Kane Terence L.
Tenney Michael P.
Wang Yun Yu
Cioffi James J.
International Business Machines - Corporation
Soward Ida M.
Zarabian Amir
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