Structure for a stacked dram capacitor

Details Structure for a stacked dram capacitor Structure for a stacked dram capacitor

1997-07-09

1999-06-08

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257301, 257303, 257308, H01L 2900

Patent

active

059106670

ABSTRACT:
A DRAM capacitor structure and its manufacturing method which includes providing a semiconductor substrate with a MOS transistor already formed above, and that the MOS transistor includes a gate and source/drain regions, then forming a first insulating layer covering the semiconductor substrate, next forming a multi-layered structure with at least one pair of alternately formed second insulating layer followed by a third insulating layer above the first insulating layer, subsequently forming an opening through the multi-layered structure and the first insulating layer exposing the source/drain region below, thereafter etching and defining a pattern on the multi-layered structure so as to expose part of the first insulating layer, this is followed by etching the second insulating layer and forming a plurality of trenches in a horizontal direction on the sidewalls of the multi-layered structure, and then forming a lower electrode layer covering the surfaces of the multi-layered structure as well as the exposed surface of the source/drain region, after that forming a dielectric layer over the lower electrode layer, and finally forming an upper electrode layer over the dielectric layer.

REFERENCES:
patent: 5077688 (1991-12-01), Kumanoya et al.
patent: 5168336 (1992-12-01), Mikoshiba
patent: 5457334 (1995-10-01), Nishimoto
patent: 5662768 (1997-09-01), Rostoker
patent: 5696395 (1997-12-01), Tseng
patent: 5783848 (1998-07-01), Chao

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