Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
1999-07-15
2001-01-30
Tran, Minh Loan (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S635000, C257S640000
Reexamination Certificate
active
06180997
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a structure for a multi-layered dielectric layer and a manufacturing method thereof, and more particularly, to a structure and a manufacturing method of multi-layered dielectric layer in which an opening with a tapered profile is formed thereon.
2. Description of Related Art
In a manufacturing process of metallization for integrated circuits, a conductive area is provided for electrical conduction, over which a plurality of conductive layers are formed for a metallization process. An opening formed between the first conductive layer and the conductive area is a contact hole. The other openings between the first conductive layer and the other conductive layers are so-called via.
A conventional process of metallization includes, at first, providing a substrate, in which possesses a conductive area. The conductive area can be a source/drain region in the substrate or a metal line. Then a dielectric layer is deposited over the conductive area. After that, a process of planarization is performed. Then the dielectric layer is etched with a photoresist mask to define an opening which is a contact hole or a via. Finally, a metal layer is deposited over the conductive area to complete a mounted structure between the metal layer and the conductive area.
Regarding the conventional process above-described, there are some problems encountered for requirements of more intensive integration of integrated circuits. Referring to
FIGS. 1
a
to
1
d
, showing cross-sectional views of several conventional methods for metallization.
Referring to
FIG. 1
a
, shown the first conventional method for metallization. A dielectric layer
102
is formed over a conductive area
100
above a substrate
1
. An opening, for example, an opening
10
is formed by a procedure of performing exposure, developing, and etching. The opening
10
possesses a nearly rectangular profile because of using an anisotropic etching. The more the integration intensity of integrated circuits, the closer the width between every two adjacent openings. When the width between the openings is decreased, the aspect ratio of the opening is correspondingly increased. It causes a bad performance of step coverage in the following process.
A structure of an overhang, for example an overhang
101
a
and an overhang
101
b
, is formed while a metal layer
104
is being deposited over the conductive area
100
.
If the metal layer
104
is continuously deposited, the adjacent overhangs in the same opening, for example, the overhangs
101
a
and
101
b
in the opening
10
is connected each other, and then a void
101
c
is formed between the overhangs
101
a
and
101
b
. The void
101
c
is uncovered while performing a planarization procedure, and then contamination materials such as polymer are formed over the conductive area
100
are dropped into the void
101
c
. It causes some problems happened in the conduction in devices of the conductive area
100
. Moreover, the overhangs formed in the openings cause the step coverage of the metal layer
104
worse, which makes the quality of the transistors in the conductive area
100
be worse.
Regarding problems caused by the rectangular structure formed by an anisotropic etching of a dry etching method, a second conventional method is provided for improving these problems. Referring to
FIG. 1
b
, a dielectric layer
112
is formed over a conductive area
110
above a substrate
1
, and then the conductive area
110
is performed exposure, developed, and etched with a photoresist layer
116
. The etching procedure is, at first, using a wet etching, and then using a dry etching. Upper portions of the openings formed in the dielectric layer
112
above the conductive area
110
are larger in diameter than lower portions of the openings, for example, a upper portion
20
a
of the opening
20
is larger in diameter than a lower portion
20
b
of the opening
20
. It will improve the problems caused by the overhangs formed in the openings in the following procedure.
The second conventional improving method causes some problems. One of these problems is that the lateral etching will consume higher percentage of planner surface budget. The consume in planner surface budget will reduce the photolithography overlayer process window during interconnect lithography process steps.
Moreover, when the integration intensity of integrated circuits increases, the openings of the dielectric layer
112
become closer. The oblique gaps formed by way of the lateral etching of the wet etching procedure can be easily connected with the adjacent opening. For example, the gap
113
in the opening
20
and the gap
114
in the opening
30
can be easily connected because that the width
112
between the gap
113
and the gap
114
is smaller than the prior art shown in
FIG. 1
a
. Such phenomena will cause the photoresist lifting at the dense contact area due to wet etching reducing adhesion area between photoresist and dielectric.
A third conventional method is provided with forming polymers on sidewalls of the dielectric layer in the openings by adjusting etching recipe. Referring to
FIG. 1
c
, at first, a conductive area
120
is formed over a substrate
1
. Then a dielectric layer
122
is formed over the conductive area
120
. By performing a procedure of exposure, developing, and etching with a photoresist layer (not shown), openings desired are formed in the dielectric layer
122
. Polymers are then formed on sidewalls of the dielectric layer
122
in all openings by adjusting the etching recipe. For example, polymers
108
are formed in the sidewalls of the dielectric layer
122
in the opening
40
as shown in
FIG. 1
c
. The polymers
108
may cause the contact metallization reliablility failure. The rate of the etching in upper portions of the opening is faster than the rate of the etching in lower portions of the opening. Therefore, an opening with oblique sidewalls can be easily formed. However, defects of the third conventional method are found that it is difficult to eliminate the polymers and the angle of the oblique sidewalls is also difficult to be controlled.
A forth conventional method is introduced by forming spacers on sidewalls of openings in a dielectric layer. Referring to
FIG. 1
d
, well-proportioned conformal spacers, for example, spacers
134
are formed on sidewalls in an opening
50
above the dielectric layer
130
. The spacers
134
can be consisted of dielectric materials, which are difficultly etched away. In the following process, the opening
50
with an oblique angle is formed owing to the protection of the spacers
134
. However, defects of the forth conventional method can be found that the spacers
134
can not be uniformly formed onto the sidewalls of the openings formed above the dielectric layer
130
. It causes an overhang structure formed on an upper portion of the sidewalls in the openings. Moreover, there are some defects such as poor capability of step cover, limitation of a ratio of height and width, a higher cost and reducing the diameter of the contact hole.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a manufacturing method and a structure of a multi-layered dielectric layer for forming openings in the dielectric layers for improving integration of integrated circuits, capability of step coverage, and problems caused by a structure of overhang.
It is another an objective of the present invention to provide a manufacturing method and a structure of a multi-layered dielectric layer for forming openings in the dielectric layers, in which oblique sidewalls of the openings in multi-layered dielectric layer can improve the step coverage in the following manufacturing process.
In accordance with the foregoing and other objectives of the present invention, the invention provides a manufacturing method of forming openings of a multi-layered dielectric layer. The method comprises steps of, at first, providing a substrate, and a conductive area is formed
Hu Shouxiang
Huang Jiawei
J.C. Patents
Tran Minh Loan
Winbond Electronics Corp.
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