Structure for a latchup robust array I/O using through wafer...

Details Structure for a latchup robust array I/O using through wafer... Structure for a latchup robust array I/O using through wafer...

2008-03-06

2010-12-21

Landau, Matthew C (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S357000, C257SE27063

Reexamination Certificate

active

07855420

ABSTRACT:
A design structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.

REFERENCES:
patent: 7498622 (2009-03-01), Chapman et al.
Notice of Allowance (Mail Date Feb. 12, 2010) for U.S. Appl. No. 11/956,386, Filing Date Dec. 14, 2007.

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