Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-01-05
2001-03-13
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S309000
Reexamination Certificate
active
06201273
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to the fabrication of capacitors in dynamic random access memory (DRAM) cells and more particularly to a structure and a method for fabricating capacitors with a large capacitance.
2) Description of the Prior Art
In dynamic semiconductor memory storage devices it is essential that storage node capacitor cell plates be large enough to retain an adequate voltage level in spite of parasitic capacitances and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. The issue of maintaining storage node capacities is particularly important as the density of DRAM cells continues to increase for future generations of memory devices. The ability to densely pack storage cells while maintaining required storage capabilities is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
The array of storage cells on a dynamic random access memory (DRAM) chip is one circuit element experiencing electrical limitations. These individual DRAM storage cells, usually consisting of a single metal-oxide-semiconductor field-effect-transistor (MOSFET) and a single capacitor are used extensively in the electronic industry for storing data. A single DRAM cell stores a bit of data on the capacitor as electrical charge. The decrease in cell capacitance caused by reduced memory cell area is a serious obstacle to increasing packing density in dynamic random access memories (DRAMs). Thus, the problem of decreased cell capacitance must be solved to achieve higher packing density in a semiconductor memory device, since decreased cell capacitance degrades read-out capability and increases the soft error rate of the memory cell as well as consumes excessive power during low-voltage operation by impeding device operation.
Generally, in a 64 MB DRAM having a 1.5 &mgr;m
2
memory cell area employing an ordinary two dimensional stacked capacitor cell, sufficient cell capacitance cannot be obtained even though a higher dielectric constant material, e.g., tantalum oxide (Ta
2
O
5
), is used. Therefore, stacked capacitors having a three-dimensional structure have been suggested to improve cell capacitance. Such stacked capacitors include, for example double-stacked, fin-structured, cylindrical, spread-stacked, and box structured capacitors. In order to increase the surface area of the capacitor, there have also been proposed methods of forming a capacitor with a pin structure extending throughout a multi-layer structure of the capacitor to connect the layers with one another and a method of forming a capacitor using a hemispherical grain polysilicon (HSG) process using polysilicon grains.
Workers in the art are aware of the limitation of capacitors and have attempted to resolve them. U.S. Pat. No. 5,364,809 (Kwon et al.) teaches a method of fabricating a multi-chamber type capacitor. A stacked capacitor having a concave area is formed and then oxide spacers are formed in the concave area. U.S. Pat. No. 5,266,513 (Frazan et al.) teaches a method to form a stacked multi-fingered cell capacitor and extension over an adjacent cell. U.S. Pat. No. 5,451,539 (Ryou) teaches a method of forming a double wall cylindrical capacitor. Ryou forms the two upright walls as spacers on an oxide cylinder. However, many of the prior art methods require substantially more processing steps or/and planar structures that make the manufacturing process more complex and costly. Therefore, it is very desirable to develop processes that are as simple as possible and maximize the capacitance per unit area. There is a challenge to develop methods of manufacturing these capacitors that minimize the manufacturing costs and maximize the device yields. In particular, there is a challenge to develop a method which minimizes the number of photoresist masking operations and provides maximum process tolerance to maximize product yields.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide methods for fabricating double wall tub or cup shaped capacitors which have less photolithographic and etch steps than the conventional processes.
It is an object of the present invention to provide methods for fabricating (DRAM) having double wall tub and cup shaped capacitors with a high density and capacitance.
It is another object of the present invention to provide structures for double wall tub and cup shaped capacitors with a high density and capacitance.
To accomplish the above objectives, the present invention provides two structures and methods of making a double wall capacitor for a dynamic random access memory (DRAM). The first embodiment provides a double square wall tub structured capacitor (right angled outer wall) and the second embodiment provides a double wall cup shaped capacitor (curved outer wall). The first embodiment uses only three photo masks to form the double wall capacitor having an outer cylinder with a right angle bend. The second embodiment uses only two photo masks to form a double wall capacitor with a curved outer cylinder.
In the first embodiment for a tub structured capacitor, the method uses a mask to form a tub shaped hole partial through an insulating layer and another mask to form a concentric contact hole over the source. A polysilicon layer is formed in the tub shaped hole and contact hole. Oxide and polysilicon spacers are sequentially formed on the sidewalls of the polysilicon layer. A third mask is used to remove the polysilicon between adjacent electrodes. The oxide spacers are then removed. The dielectric layer and top electrode are formed next thus completing the double wall tub shaped capacitor.
In slightly more detail, the first embodiment provides a method of fabricating a capacitor having a double wall tub shaped storage electrode (with a right angled base) for a memory device on a substrate. The substrate has a device area with a source region formed therein. A first insulating layer composed of silicon oxide is formed on a device area and elsewhere over the substrate. The first insulating layer is patterned to form a contact hole to partially expose the source region. An upper portion of the first insulation layer centered around the contact hole is removed to form a tub shaped hole centered over the contact hole. The cup hole has vertical sidewalls and a horizontal bottom. A first conductive layer composed of polysilicon is formed over the first insulating layer, in the cup hole, and in the contact hole. The first conductive layer has vertical sidewalls on the vertical sidewalls of the cup hole. Subsequently oxide spacers are formed over the vertical sidewalls of the cylindrical storage electrode. Next, the first conductive layer is patterned to separate adjacent storage electrodes. A vertical inner wall of polysilicon is then formed on the vertical sidewalls of the spacers. The spacers and the first insulation layer are removed forming a the double wall tub shaped storage electrode aligned to the device area. A capacitor dielectric layer and a top electrode are formed over at least the storage electrode thereby forming the double wall tub shaped capacitor.
The second embodiment for forming a double wall cup shaped capacitor comprises forming a first insulating layer composed of silicon oxide the device area and over a substrate. A first photo resist layer is formed having a first opening over a source region. Optionally, the first insulation layer is anisotropically etched an adjustable depth. Then, the first insulation layer is isotropically etched through the first opening forming a cup shaped hole. The cup shaped hole has an adjustable shape which is affected by the previous optional anisotropic etch. The first insulating layer is anisotropically etched through the first opening forming a contact hole to partially expose the source. The photoresist layer is then removed. A conformal firs
Liang Mong-Song
Wang Chen-Jong
Ackerman Stephen B.
Prenty Mark V.
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company
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