Structure and system-on-chip integration of a two-transistor...

Details Structure and system-on-chip integration of a two-transistor... Structure and system-on-chip integration of a two-transistor...

2005-01-18

2005-01-18

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S189040, C365S230050

Reexamination Certificate

active

06845033

ABSTRACT:
A two-port dynamic random access memory (DRAM) cell consisting of two transistors and two trench capacitors (2T and 2C DRAM cell) connecting two one transistor and one capacitor DRAM cell (1T DRAM cell) is described. The mask data and cross-section of the 2T 2C DRAM and 1T DRAM cells are fully compatible to each other except for the diffusion connection that couples two storage nodes of the two 1T DRAM cells. This allows a one-port memory cell with 1T and 1C DRAM cell and a two-port memory cell with 2T and 2C DRAM cell to be fully integrated, forming a true system-on chip architecture. Alternatively, by halving the capacitor, the random access write cycle time is further reduced, while still maintaining the data retention time. The deep trench process time is also reduced by reducing by one-half the trench depth.

REFERENCES:
patent: 5406510 (1995-04-01), Mihara et al.
patent: 6169684 (2001-01-01), Takahashi et al.
patent: 6552951 (2003-04-01), Raj et al.
patent: 6711050 (2004-03-01), Sadakata

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